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1 ? 2003 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-5998/3 november 2003 2.5v multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 bits and 2,359,296 bits idt and the idt logo are registered trademarks of integrated device technology, inc commercial and industrial temperature ranges advance information IDT72T51546 idt72t51556 features: ? ? ? ? ? choose from among the following memory density options: IDT72T51546 ? ? ? ? ? total available memory = 1,179,648 bits idt72t51556 ? ? ? ? ? total available memory = 2,359,296 bits ? ? ? ? ? configurable from 1 to 32 queues ? ? ? ? ? queues may be configured at master reset from the pool of total available memory in blocks of 256 x 36 ? ? ? ? ? independent read and write access per queue ? ? ? ? ? user programmable via serial port ? ? ? ? ? user selectable i/o: 2.5v lvttl, 1.5v hstl, 1.8v ehstl ? ? ? ? ? default multi-queue device configurations ? IDT72T51546 : 1,024 x 36 x 32q ? idt72t51556 : 2,048 x 36 x 32q ? ? ? ? ? 100% bus utilization, read and write on every clock cycle ? ? ? ? ? 200 mhz high speed operation (5ns cycle time) ? ? ? ? ? 3.6ns access time ? ? ? ? ? echo read enable & echo read clock outputs ? ? ? ? ? individual, active queue flags ( ov , ff , pae , paf , pr ) ? ? ? ? ? 8 bit parallel flag status on both read and write ports ? ? ? ? ? shows pae and paf status of 8 queues ? ? ? ? ? direct or polled operation of flag status bus ? ? ? ? ? global bus matching - (all queues have same input bus width and output bus width) ? ? ? ? ? user selectable bus matching options: ? x36in to x36out ? x18in to x36out ? x9in to x36out ? x36in to x18out ? x36in to x9out ? ? ? ? ? fwft mode of operation on read port ? ? ? ? ? packet mode operation ? ? ? ? ? partial reset, clears data in single queue ? ? ? ? ? expansion of up to 8 multi-queue devices in parallel is available ? ? ? ? ? power down input provides additional power savings in hstl and ehstl modes. ? ? ? ? ? jtag functionality (boundary scan) ? ? ? ? ? available in a 256-pin pbga, 1mm pitch, 17mm x 17mm ? ? ? ? ? high performance submicron cmos technology ? ? ? ? ? industrial temperature range (-40c to +85c) is available q0 q1 q2 q31 multi-queue flow-control device fstr wen paf ff wradd waden wclk paf n x36 data in estr eren pae pr rdadd raden erclk pae n x36 data out oe ov write control d in q out pr n 8 8 8 8 read control write flags read flags 5998 drw01 ren rclk functional block diagram
2 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits description: the IDT72T51546/72t51556 multi-queue flow-control devices is a single chip within which anywhere between 1 and 32 discrete fifo queues can be setup. all queues within the device have a common data input bus, (write port) and a common data output bus, (read port). data written into the write port is directed to a respective queue via an internal de-multiplex operation, ad- dressed by the user. data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. data writes and reads can be performed at high speeds up to 200mhz, with access times of 3.6ns. data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously. the device provides full flag and output valid flag status for the queue selected for write and read operations respectively. also a programmable almost full and programmable almost empty flag for each queue is provided. two 8 bit programmable flag busses are available, providing status of queues not selected for write or read operations. when 8 or less queues are configured in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a polled or direct mode of bus operation provides the flag busses with all queues status. bus matching is available on this device, either port can be 9 bits, 18 bits or 36 bits wide provided that at least one port is 36 bits wide. when bus matching is used the device ensures the logical transfer of data throughput in a little endian manner. a packet mode of operation is also provided when the device is configured for 36 bit input and 36 bit output port sizes. the packet mode provides the user with a flag output indicating when at least one (or more) packets of data within a queue is available for reading. the packet ready provides the user with a means by which to mark the start and end of packets of data being passed through the queues. the multi-queue device then provides the user with an internally generated packet ready status per queue. the user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 32, the individual queue depths being independent of each other. the programmable flag positions are also user programmable. all programming is done via a dedicated serial port. if the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. both master reset and partial reset pins are provided on this device. a master reset latches in all configuration setup pins and must be performed before programming of the device can take place. a partial reset will reset the read and write pointers of an individual queue, provided that the queue is selected on both the write port and read port at the time of partial reset. echo read enable, eren and echo read clock, erclk outputs are provided. these are outputs from the read port of the queue that are required for high speed data communication, to provide tighter synchronization between the data being transmitted from the qn outputs and the data being received by the input device. data read from the read port is available on the output bus with respect to eren and erclk, this is very useful when data is being read at high speed. the multi-queue flow-control device has the capability of operating its io in either 2.5v lvttl, 1.5v hstl or 1.8v ehstl mode. the type of io is selected via the iosel input. the core supply voltage (v cc ) to the multi-queue is always 2.5v, however the output levels can be set independently via a separate supply, v ddq . the devices also provide additional power savings via a power down input. this input disables the write port data inputs when no write operations are required. a jtag test port is provided, here the multi-queue flow-control device has a fully functional boundary scan feature, compliant with ieee 1149.1 standard test access port and boundary scan architecture. see figure 1, multi-queue flow-control device block diagram for an outline of the functional blocks within the device.
3 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges oe x9, x18, x36 q out output register q 0 - q 35 wradd waden input demux wclk wen write control logic d in write pointers active q flags paf general flag monitor fstr paf n ff fsync paf reset logic serial multi-queue program- ming pae / paf offset tms tdi tdo tck trst fm iw ow bm prs mrs si so sclk seni rclk ren read control logic read pointers active q flags pae general flag monitor estr ov esync rdadd raden df fxo fxi exi exo 5998 drw02 x9, x18, x36 8 8 8 id0 id1 id2 device id 3 bit pkt packet mode logic jtag logic d 35 = teop d 34 = tsop 2 q 35 = reop q 34 = rsop 2 pr pr n/ pae n 8 seno dfm mast pae upto 32 fifo queues 2.3 mbit dual port memory output mux d 0 - d 35 null-q erclk eren io level control & power down iosel vref pd figure 1. multi-queue flow-control device block diagram
4 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits advance information d14 a d13 d12 d10 q9 d7 q6 d4 q3 d1 id1 tck tdo q12 q14 q15 d15 b d16 d11 d9 q8 d6 q5 d3 q2 d0 id0 tms tdi q11 q13 q19 d17 c d18 d19 d8 q7 d5 q4 d2 q1 trst q0 iosel id2 q10 q17 q18 d20 d d21 d22 v ddq v ddq v ddq v ddq v ddq v ddq v cc v cc v cc v cc q16 q21 q20 d23 e d24 d25 v ddq v ddq v ddq v ddq v cc v cc v cc v cc gnd gnd q24 q23 q22 d26 f d27 d28 v ddq v ddq v cc v cc gnd gnd gnd gnd gnd gnd q27 q26 q25 d29 g d30 d31 v cc v cc v cc v cc gnd gnd gnd gnd gnd gnd q30 q29 q28 d32 h d33 d34 v cc v cc gnd gnd gnd gnd gnd gnd gnd gnd q33 q32 q31 gnd j null-q d35 v cc v cc gnd gnd gnd gnd gnd gnd gnd gnd pkt q35 q34 pd k gnd vref v cc v cc v cc v cc gnd gnd gnd gnd gnd gnd gnd mast fm si l dfm df v ddq v ddq v cc v cc gnd gnd gnd gnd gnd gnd bm iw ow seno m seni so v ddq v ddq v ddq v ddq v cc v cc v cc v cc gnd gnd oe rdadd0 rdadd1 wradd1 n wradd0 sclk v ddq v ddq v ddq v ddq v ddq v ddq v cc v cc v cc v cc rdadd2 rdadd3 rdadd4 wradd4 p wradd3 wradd2 waden pae 3 paf 3 pae 6 paf 6 pae 7 paf 7 pae ff ov rdadd5 rdadd6 rdadd7 wradd6 r wradd5 fsync fstr pae 2 paf 2 pae 5 paf 5 eren paf 4 erclk paf pr raden estr esync wradd7 t fxi fxo paf 0 pae 1 paf 1 pae 4 wen ren wclk rclk prs mrs pae 0 12 3 4 13 512 611 710 8 9 14 15 16 5998 drw03 a1 ball pad corner exo exi pin configuration pbga (bb256-1, order code: bb) top view
5 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges detailed description multi-queue structure the idt multi-queue flow-control device has a single data input port and single data output port with up to 32 fifo queues in parallel buffering between the two ports. the user can setup between 1 and 32 queues within the device. these queues can be configured to utilize the total available memory, providing the user with full flexibility and ability to configure the queues to be various depths, independent of one another. memory organization/ allocation the memory is organized into what is known as ?blocks?, each block being 256 x36 bits. when the user is configuring the number of queues and individual queue sizes the user must allocate the memory to respective queues, in units of blocks, that is, a single queue can be made up from 0 to m blocks, where m is the total number of blocks available within a device. also the total size of any given queue must be in increments of 256 x36. for the IDT72T51546 and idt72t51556 the total available memory is 128 and 256 blocks respectively (a block being 256 x36). queues can be built from these blocks to make any size queue desired and any number of queues desired. bus widths the input port is common to all queues within the device, as is the output port. the device provides the user with bus matching options such that the input port and output port can be either x9, x18 or x36 bits wide provided that at least one of the ports is x36 bits wide, the read and write port widths being set independently of one another. because the ports are common to all queues the width of the queues is not individually set, so that the input width of all queues are equal and the output width of all queues are equal. writing to & reading from the multi-queue data being written into the device via the input port is directed to a discrete queue via the write queue select address inputs. conversely, data being read from the device read port is read from a queue selected via the read queue select address inputs. data can be simultaneously written into and read from the same queue or different queues. once a queue is selected for data writes or reads, the writing and reading operation is performed in the same manner as a conventional idt synchronous fifo, utilizing clocks and enables, there is a single clock and enable per port. when a specific queue is addressed on the write port, data placed on the data inputs is written to that queue sequentially based on the rising edge of a write clock provided setup and hold times are met. conversely, data is read on to the output port after an access time from a rising edge on a read clock. the operation of the write port is comparable to the function of a conventional fifo operating in standard idt mode. write operations can be performed on the write port provided that the queue currently selected is not full, a full flag output provides status of the selected queue. the operation of the read port is comparable to the function of a conventional fifo operating in fwft mode. when a queue is selected on the output port, the next word in that queue will automatically fall through to the output register. all subsequent words from that queue require an enabled read cycle. data cannot be read from a selected queue if that queue is empty, the read port provides an output valid flag indicating when data read out is valid. if the user switches to a queue that is empty, the last word from the previous queue will remain on the output register. as mentioned, the write port has a full flag, providing full status of the selected queue. along with the full flag a dedicated almost full flag is provided, this almost full flag is similar to the almost full flag of a conventional idt fifo. the device provides a user programmable almost full flag for all 32 queues and when a respective queue is selected on the write port, the almost full flag provides status for that queue. conversely, the read port has an output valid flag, providing status of the data being read from the queue selected on the read port. as well as the output valid flag the device provides a dedicated almost empty flag. this almost empty flag is similar to the almost empty flag of a conventional idt fifo. the device provides a user programmable almost empty flag for all 32 queues and when a respective queue is selected on the read port, the almost empty flag provides status for that queue. programmable flag busses in addition to these dedicated flags, full & almost full on the write port and output valid & almost empty on the read port, there are two flag status busses. an almost full flag status bus is provided, this bus is 8 bits wide. also, an almost empty flag status bus is provided, again this bus is 8 bits wide. the purpose of these flag busses is to provide the user with a means by which to monitor the data levels within queues that may not be selected on the write or read port. as mentioned, the device provides almost full and almost empty registers (programmable by the user) for each of the 32 queues in the device. in the IDT72T51546/72t51556 multi-queue flow-control devices the user has the option of utilizing anywhere between 1 and 32 queues, therefore the 8 bit flag status busses are multiplexed between the 32 queues, a flag bus can only provide status for 8 of the 32 queues at any moment, this is referred to as a ?quadrant?, such that when the bus is providing status of queues 1 through 8, this is quadrant 1, when it is queues 9 through 16, this is quadrant 2 and so on up to quadrant 4. if less than 32 queues are setup in the device, there are still 4 quadrants, such that in ?polled? mode of operation the flag bus will still cycle through 4 quadrants. if for example only 22 queues are setup, quadrants 1 and 2 will reflect status of queues 1 through 8 and 9 through 16 respectively. quadrant 3 will reflect the status of queues 17 through 22 on the least significant 6 bits, the most significant 2 bits of the flag bus are don?t care and the 4th quadrant outputs will be don?t care also. the flag busses are available in two user selectable modes of operation, ?polled? or ?direct?. when operating in polled mode a flag bus provides status of each quadrant sequentially, that is, on each rising edge of a clock the flag bus is updated to show the status of each quadrant in order. the rising edge of the write clock will update the almost full bus and a rising edge on the read clock will update the almost empty bus. the mode of operation is always the same for both the almost full and almost empty flag busses. when operating in direct mode, the quadrant on the flag bus is selected by the user. so the user can actually address the quadrant to be placed on the flag status busses, these flag busses operate independently of one another. addressing of the almost full flag bus is done via the write port and addressing of the almost empty flag bus is done via the read port. packet ready the multi-queue flow-control device also offers a ?packet mode? operation. packet mode is user selectable and requires the device to be configured with both write and read ports as 36 bits wide. in packet mode, users can define the length of packets or frame by using the two most significant bits of the 36-bit word. bit 34 is used to mark the start of packet (sop) and bit 35 is used to mark the end of packet (eop) as shown in table 5). when writing data into a given queue , the first word being written is marked, by the user setting bit 34 as the ?start of packet? (sop) and the last word written is marked as the ?end of packet? (eop) with all words written between the start of packet (sop) marker (bit 34) and the end of packet (eop) packet marker (bit 35) constituting the entire packet. a packet can be any length the user desires, up to the total available memory in the multi-queue device. the device monitors the sop (bit 34) and looks for the word that contains the eop (bit 35). the read port is supplied with an additional
6 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits status flag, ?packet ready?. the packet ready ( pr ) flag in conjunction with output valid ( ov ) indicates when at least one packet is available to read. when in packet mode the almost empty flag status , provides packet ready flag status for individual queues. expansion expansion of multi-queue devices is also possible, up to 8 devices can be connected in a parallel fashion providing the possibility of both depth expansion or queue expansion. depth expansion means expanding the depths of individual queues. queue expansion means increasing the total number of queues available. depth expansion is possible by virtue of the fact that more memory blocks within a multi-queue device can be allocated to increase the depth of a queue. for example, depth expansion of 8 devices provides the possibility of 8 queues of 64k x36 deep, each queue being setup within a single device utilizing all memory blocks available to produce a single queue. this is the deepest queue that can setup within a device. for queue expansion a maximum number of 256 (8 x 32) queues may be setup, each queue being 2k x36 deep, if less queues are setup, then more memory blocks will be available to increase queue depths if desired. when connecting multi-queue devices in expansion mode all respective input pins (data & control) and output pins (data & flags), should be ?connected? together between individual devices.
7 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges bm bus matching lvttl this pin is setup before master reset and must not toggle during any device operation. this pin is used (l14) input along with iw and ow to setup the multi-queue flow-control device bus width. please refer to table 3 for details. d[35:0] data input bus hstl-lvttl these are the 36 data input pins. data is written into the device via these input pins on the ri sing edge din input of wclk provided that wen is low. note, that in packet mode d32-d35 may be used as packet (see pin no. markers, please see packet ready functional discussion for more detail. due to bus matching not all inputs table for details) may be used, any unused inputs should be tied low. df (1) default flag lvttl if the user requires default programming of the multi-queue device, this pin must be setup before master (l3) input reset and must not toggle during any device operation. the state of this input at master reset determines the value of the pae / paf flag offsets. if df is low the value is 8, if df is high the value is 128. dfm (1) default mode lvttl the multi-queue device requires programming after master reset. the user can do this serially via the (l2) input serial port, or the user can use the default method. if dfm is low at master reset then serial mode will be selected, if high then default mode is selected. erclk rclk echo hstl-lvttl read clock echo output, this output generates a clock based on the read clock input, this is used for source (r10) output synchronous clocking where the receiving devices utilizes the erclk to clock data output from the queue. eren ren echo hstl-lvttl read enable echo output, can be used in conjunction with the erclk output to load data output from the (r11) output queue into the receiving device. estr pae n flag bus lvttl if direct operation of the pae n bus has been selected, the estr input is used in conjunction with rclk (r15) strobe input and the rdadd bus to select a quadrant of queues to be placed on to the pae n bus outputs. a quadrant addressed via the rdadd bus is selected on the rising edge of rclk provided that estr is high. if polled operations has been selected, estr should be tied inactive, low. note, that a pae n flag bus selection cannot be made, (estr must not go active) until programming of the part has been completed and seno has gone low. esync pae n bus sync hstl-lvttl esync is an output from the multi-queue device that provides a synchronizing pulse for the pae n bus (r16) output during polled operation of the pae n bus. during polled operation each quadrant of queue status flags is loaded on to the pae n bus outputs sequentially based on rclk. the first rclk rising edge loads quadrant 1 on to pae n, the second rclk rising edge loads quadrant 2 and so on. the fifth rclk rising edge will again load quadrant 1. during the rclk cycle that quadrant 1 of a selected device is placed on to the pae n bus, the esync output will be high. for all other quadrants of that device, the esync output will be low. exi pae n bus lvttl the exi input is used when multi-queue devices are connected in expansion mode and polled pae n (t16) expansion in input bus operation has been selected . exi of device ?n? connects directly to exo of device ?n-1?. the exi receives a token from the previous device in a chain. in single device mode the exi input must be tied low if the pae n bus is operated in direct mode. if the pae n bus is operated in polled mode the exi input must be connected to the exo output of the same device. in expansion mode the exi of the first device should be tied low, when direct mode is selected. exo pae n bus lvttl exo is an output that is used when multi-queue devices are connected in expansion mode and polled (t15) expansion out output pae n bus operation has been selected . exo of device ?n? connects directly to exi of device ?n+1?. this pin pulses when device n has placed its final (4th) quadrant on to the pae n bus with respect to rclk. this pulse (token) is then passed on to the next device in the chain ?n+1? and on the next rclk rising edge the first quadrant of device n+1 will be loaded on to the pae n bus. this continues through the chain and exo of the last device is then looped back to exi of the first device. the esync output of each device in the chain provides synchronization to the user of this looping event. ff full flag hstl-lvttl this pin provides the full flag output for the active queue, that is, the queue selected on the input port (p8) output for write operations, (selected via wclk, wradd bus and waden). on the wclk cycle after a queue selection, this flag will show the status of the newly selected queue. data can be written to this queue on the next cycle provided ff is high. this flag has high-impedance capability, this is important during expansion of devices, when the ff flag output of up to 8 devices may be connected together on a common line. the device with a queue selected takes control of the ff bus, all other devices place their ff output into high-impedance. when a queue selection is made on the write port this output will switch from high-impedance control on the next wclk cycle. this flag is synchronized to wclk. pin descriptions symbol & name i/o type description pin no.
8 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits pin descriptions (continued) fm (1) flag mode hstl-lvttl this pin is setup before a master reset and must not toggle during any device operation. the state of the (k16) input fm pin during master reset will determine whether the paf n and pae n flag busses operate in either polled or direct mode. if this pin is high the mode is polled, if low then it will be direct. fstr paf n flag bus lvttl if direct operation of the paf n bus has been selected, the fstr input is used in conjunction with wclk (r4) strobe input and the wradd bus to select a quadrant of queues to be placed on to the paf n bus outputs. a quadrant addressed via the wradd bus is selected on the rising edge of wclk provided that fstr is high. if polled operations has been selected, fstr should be tied inactive, low. note, that a paf n flag bus selection cannot be made, (fstr must not go active) until programming of the part has been completed and seno has gone low. fsync paf n bus sync lvttl fsync is an output from the multi-queue device that provides a synchronizing pulse for the paf n bus (r3) output during polled operation of the paf n bus. during polled operation each quadrant of queue status flags is loaded on to the paf n bus outputs sequentially based on wclk. the first wclk rising edge loads quadrant 1 on to paf n, the second wclk rising edge loads quadrant 2 and so on. the fifth wclk rising edge will again load quadrant 1. during the wclk cycle that quadrant 1 of a selected device is placed on to the paf n bus, the fsync output will be high. for all other quadrants of that device, the fsync output will be low. fxi paf n bus lvttl the fxi input is used when multi-queue devices are connected in expansion mode and polled paf n (t2) expansion in input bus operation has been selected . fxi of device ?n? connects directly to fxo of device ?n-1?. the fxi receives a token from the previous device in a chain. in single device mode the fxi input must be tied low if the paf n bus is operated in direct mode. if the paf n bus is operated in polled mode the fxi input must be connected to the fxo output of the same device. in expansion mode the fxi of the first device should be tied low, when direct mode is selected. fxo paf n bus lvttl fxo is an output that is used when multi-queue devices are connected in expansion mode and polled (t3) expansion out output paf n bus operation has been selected . fxo of device ?n? connects directly to fxi of device ?n+1?. this pin pulses when device n has placed its final (4th) quadrant on to the paf n bus with respect to wclk. this pulse (token) is then passed on to the next device in the chain ?n+1? and on the next wclk rising edge the first quadrant of device n+1 will be loaded on to the paf n bus. this continues through the chain and fxo of the last device is then looped back to fxi of the first device. the fsync output of each device in the chain provides synchronization to the user of this looping event. id[2:0] (1) device id pins hstl-lvttl for the 32q multi-queue device the wradd and rdadd address busses are 8 bits wide. when a queue id2-c9 input selection takes place the 3 msb?s of this 8 bit address bus are used to address the specific device (the id1-a10 5 lsb?s are used to address the queue within that device). during write/read operations the 3 msb?s id0-b10 of the address are compared to the device id pins. the first device in a chain of multi-queue?s (connected in expansion mode), may be setup as ?000?, the second as ?001? and so on through to device 8 which is ?111?, however the id does not have to match the device order. in single device mode these pins should be setup as ?000? and the 3 msb?s of the wradd and rdadd address busses should be tied low. the id[2:0] inputs setup a respective devices id during master reset. these id pins must not toggle during any device operation. note, the device selected as the ?master? does not have to have the id of ?000?. iosel io select lvttl this pin is used to select either hstl or 2.5v lvttl operation for the i/o. if hstl or ehstl i/o are (c8) input required then iosel should be tied high. if lvttl i/o are required then it should be tied low. iw (1) input width lvttl this pin is used in conjunction with ow and bm to setup the input and output bus widths to be a combination (l15) input of x9, x18 or x36, (providing that one port is x36). mast (1) master device hstl-lvttl the state of this input at master reset determines whether a given device (within a chain of devices), is the (k15) input master device or a slave. if this pin is high, the device is the master if it is low then it is a slave. the master device is the first to take control of all outputs after a master reset, all slave devices go to high- impedance, preventing bus contention. if a multi-queue device is being used in single device mode, this pin must be set high. mrs master reset hstl-lvttl a master reset is performed by taking mrs from high to low, to high. device programming is required (t9) input after master reset. null-q null queue hstl-lvttl this pin is used on the read port when a null-q is required, it is used in conjunction with the rdadd (j2) select input and raden address bus to address the null-q. symbol & name i/o type description pin no.
9 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges oe output enable hstl-lvttl the output enable signal is an asynchronous signal used to provide three-state control of the multi-queue (m14) input data output bus, qout. if a device has been configured as a ?master? device, the qout data outputs will be in a low impedance condition if the oe input is low. if oe is high then the qout data outputs will be in high impedance. if a device is configured a ?slave? device, then the qout data outputs will always be in high impedance until that device has been selected on the read port, at which point oe provides three- state of that respective device. ov output valid hstl-lvttl this output flag provides output valid status for the data word present on the multi-queue flow-control device (p9) flag output data output port, qout. this flag is therefore, 2-stage delayed to match the data output path delay. that is, there is a 2 rclk cycle delay from the time a given queue is selected for reads, to the time the ov flag represents the data in that respective queue. when a selected queue on the read port is read to empty, the ov flag will go high, indicating that data on the output bus is not valid. the ov flag also has high-impedance capability, required when multiple devices are used and the ov flags are tied together. ow (1) output width lvttl this pin is setup during master reset and must not toggle during any device operation. this pin is used (l16) input in conjunction with iw and bm to setup the data input and output bus widths to be a combination of x9, x18 or x36, (providing that one port is x36). pae programmable hstl-lvttl this pin provides the almost-empty flag status for the queue that has been selected on the output port (p10) almost-empty output for read operations, (selected via rclk, rdadd and raden). this pin is low when the selected flag queue is almost-empty. this flag output may be duplicated on one of the pae n bus lines. this flag is synchronized to rclk. pae n/ pr n programmable hstl-lvttl on the 32q device the pae n/ pr n bus is 8 bits wide. during a master reset this bus is setup for either ( pae 7-p11 almost-empty output almost empty mode or packet mode. this output bus provides pae / pr n status of 8 queues (1 quadrant), pae 6-p12 flag bus/packet within a selected device, having a total of 4 quadrants. during queue read/write operations these outputs pae 5-r12 readyflag bus provide programmable empty flag status or packet ready status, in either direct or polled mode. the mode pae 4-t12 of flag operation is determ ined during master reset via the state of the fm input. this flag bus is capable of pae 3-p13 high-impedance state, this is important during expansion of multi-queue devices. during direct operation pae 2-r13 the pae n/ pr n bus is updated to show the pae / pr status of a quadrant of queues within a selected device. pae 1-t13 selection is made using rclk, estr and rdadd. during polled operation the pae n/ pr n bus is pae 0-t14) loaded with the pae / pr n status of multi-queue flow-control quadrants sequentially based on the rising edge of rclk. pae or pr operation is determined by the state of pkt during master reset. paf programmable hstl-lvttl this pin provides the almost-full flag status for the queue that has been selected on the input port for (r8) almost-full flag output write operations, (selected via wclk, wradd and waden). this pin is low when the selected queue is almost-full. this flag output may be duplicated on one of the paf n bus lines. this flag is synchronized to wclk. paf n programmable hstl-lvttl on the 32q device the paf n bus is 8 bits wide. at any one time this output bus provides paf status ( paf 7-p7 almost-full flag output of 8 queues (1 quadrant), within a selected device, having a total of 4 quadrants. during queue read/ paf 6-p6 bus write operations these outputs provide programmable full flag status, in either direct or polled mode. the paf 5-r6 mode of flag operation is determined during master reset via the state of the fm input. this flag bus is paf 4-r7 capable of high-impedance state, this is important during expansion of multi-queue devices. during direct paf 3-p5 operation the paf n bus is updated to show the paf status of a quadrant of queues within a selected paf 2-r5 device. selection is made using wclk, fstr, wradd and waden. during polled operation the paf n paf 1-t5 bus is loaded with the paf status of multi-queue flow-control quadrants sequentially based on the rising paf 0-t4) edge of wclk. pd power down hstl this input is used to provide additional power savings. when the device i/o is setup for hstl/ehstl (k1) input mode a high on the pd input disables the data inputs on the write port only, providing significant power savings. in lvttl mode this pin has no operation pkt (1) packet mode lvttl the state of this pin during a master reset will determine whether the part is operating in packet mode (j14) input providing both a packet ready ( pr ) output and a programmable almost empty ( pae ) discrete output, or standard mode, providing a ( pae ) output only. if this pin is high during master reset the part will operate in packet mode, if it is low then almost empty mode. if packet mode has been selected the read port flag bus becomes packet ready flag bus, pr n and the discrete packet ready flag, pr is functional. if almost empty operation has been selected then the flag bus provides almost empty status, pae n and pin descriptions (continued) symbol & name i/o type description pin no.
10 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits pin descriptions (continued) pkt (1) packet mode lvttl the discrete almost empty flag, pae is functional, the pr flag is inactive and should not be connected. (continued) input packet ready utilizes user marked locations to identify start and end of packets being written into the (j14) device. packet mode can only be selected if both the input port width and output port width are 36 bits. pr packet ready hstl-lvttl if packet mode has been selected this flag output provides packet ready status of the queue selected (r9) flag output for read operations. during a master reset the state of the pkt input determines whether packet mode of operation will be used. if packet mode is selected, then the condition of the pr flag and ov signal are asserted indicates a packet is ready for reading. the user must mark the start of a packet and the end of a packet when writing data into a queue. using these start of packet (sop) and end of packet (eop) markers, the multi-queue device sets pr low if one or more ?complete? packets are available in the queue. a complete packet(s) must be written before the user is allowed to switch queues. prs partial reset hstl-lvttl a partial reset can be performed on a single queue selected within the multi-queue device. before a partial (t8) input reset can be performed on a queue, that queue must be selected on both the write port and read port 2 clock cycles before the reset is performed. a partial reset is then performed by taking prs low for one wclk cycle and one rclk cycle. the partial reset will only reset the read and write pointers to the first memory location, none of the devices configuration will be changed. q[35:0] data output bus hstl-lvttl these are the 36 data output pins. data is read out of the device via these output pins on the rising edge qout output of rclk provided that ren is low, oe is low and the queue is selected. note, that in packet ready (see pin no. mode q32-q35 may be used as packet markers, please see packet ready functional discussion for more table for details) detail. due to bus matching not all outputs may be used, any unused outputs should not be connected. raden read address hstl-lvttl the raden input is used in conjunction with rclk and the rdadd address bus to select a queue to (r14) enable input be read from. a queue addressed via the rdadd bus is selected on the rising edge of rclk provided that raden is high. raden should be asserted (high) only during a queue change cycle(s). raden should not be permanently tied high. raden cannot be high for the same rclk cycle as estr. note, that a read queue selection cannot be made, (raden must not go active) until programming of the part has been completed and seno has gone low. rclk read clock hstl-lvttl when enabled by ren , the rising edge of rclk reads data from the selected queue via the output (t10) input bus qout. the queue to be read is selected via the rdadd address bus and a rising edge of rclk while raden is high. a rising edge of rclk in conjunction with estr and rdadd will also select the pae n/ pr n flag quadrant to be placed on the pae n/ pr n bus during direct flag operation. during polled flag operation the pae n/ pr n bus is cycled with respect to rclk and the esync signal is synchronized to rclk. the pae , pr and ov outputs are all synchronized to rclk. during device expansion the exo and exi signals are based on rclk. rclk must be continuous and free-running. rdadd read address hstl-lvttl for the 32q device the rdadd bus is 8 bits. the rdadd bus is a dual purpose address bus. the first [7:0] bus input function of rdadd is to select a queue to be read from. the least significant 5 bits of the bus, rdadd[4:0] (rdadd7-p16 are used to address 1 of 32 possible queues within a multi-queue device. the most significant 3 bits, rdadd6-p15 rdadd[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion rdadd5-p14 mode. these 3 msb?s will address a device with the matching id code. the address present on the rdadd4-n16 rdadd bus will be selected on a rising edge of rclk provided that raden is high, (note, that data rdadd3-n15 can be placed on to the qout bus, read from the previously selected queue on this rclk edge). on the rdadd2-n14 next rising rclk edge after a read queue select, a data word from the previous queue will be placed rdadd1-m16 onto the outputs, qout, regardless of the ren input. two rclk rising edges after read queue select, rdadd0-m15) data will be placed on to the qout outputs from the newly selected queue, regardless of ren due to the first word fall through effect. the second function of the rdadd bus is to select the quadrant of queues to be loaded on to the pae n/ pr n bus during strobed flag mode. the least significant 2 bits, rdadd[1:0] are used to select the quadrant of a device to be placed on the pae n bus. the most significant 3 bits, rdadd[7:5] are again used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. address bits rdadd[4:2] are don?t care during quadrant selection. the quadrant address present on the rdadd bus will be selected on the rising edge of rclk provided that estr is high, (note, that data can be placed on to the qout bus, read from the previously selected queue on this rclk edge). please refer to table 2 for details on rdadd bus. symbol & name i/o type description pin no.
11 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges pin descriptions (continued) ren read enable hstl-lvttl the ren input enables read operations from a selected queue based on a rising edge of rclk. (t11) input a queue to be read from can be selected via rclk, raden and the rdadd address bus regardless of the state of ren . data from a newly selected queue will be available on the qout output bus on the second rclk cycle after queue selection regardless of ren due to the fwft operation. a read enable is not required to cycle the pae n/ pr n bus (in polled mode) or to select the pae n quadrant , (in direct mode). sclk serial clock hstl-lvttl if serial programming of the multi-queue device has been selected during master reset, the sclk input (n3) input clocks the serial data through the multi-queue device. data setup on the si input is loaded into the device on the rising edge of sclk provided that seni is enabled, low. when expansion of devices is performed the sclk of all devices should be connected to the same source. seni serial input hstl-lvttl during serial programming of a multi-queue device, data loaded onto the si input will be clocked into the (m2) enable input part (via a rising edge of sclk), provided the seni input of that device is low. if multiple devices are cascaded, the seni input should be connected to the seno output of the previous device. so when serial loading of a given device is complete, its seno output goes low, allowing the next device in the chain to be programmed ( seno will follow seni of a given device once that device is programmed). the seni input of the master device (or single device), should be controlled by the user. seno serial output hstl-lvttl this output is used to indicate that serial programming or default programming of the multi-queue device (m1) enable output has been completed. seno follows seni once programming of a device is complete. therefore, seno will go low after programming provided seni is low, once seni is taken high again, seno will also go high. when the seno output goes low, the device is ready to begin normal read/write operations. if multiple devices are cascaded and serial programming of the devices will be used, the seno output should be connected to the seni input of the next device in the chain. when serial programming of the first device is complete, seno will go low, thereby taking the seni input of the next device low and so on throughout the chain. when a given device in the chain is fully programmed the seno output essentially follows the seni input. the user should monitor the seno output of the final device in the chain. when this output goes low, serial loading of all devices has been completed. si serial in hstl-lvttl during serial programming this pin is loaded with the serial data that will configure the multi-queue devices. (l1) input data present on si will be loaded on a rising edge of sclk provided that seni is low. in expansion mode the serial data input is loaded into the first device in a chain. when that device is loaded and its seno has gone low, the data present on si will be directly output to the so output. the so pin of the first device connects to the si pin of the second and so on. the multi-queue device setup registers are shift registers. so serial out hstl-lvttl this output is used in expansion mode and allows serial data to be passed through devices in the chain (m3) output to complete programming of all devices. the si of a device connects to so of the previous device in the chain. the so of the final device in a chain should not be connected. tck (2) jtag clock lvttl clock input for jtag function. one of four terminals required by ieee standard 1149.1-1990. test (a8) input operations of the device are synchronous to tck. data from tms and tdi are sampled on the rising edge of tck and outputs change on the falling edge of tck. if the jtag function is not used this signal needs to be tied to gnd. tdi (2) jtag test data lvttl one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan operation, (b9) input input test data serially loaded via the tdi on the rising edge of tck to either the instruction register, id register and bypass register. an internal pull-up resistor forces tdi high if left unconnected. tdo (2) jtag test data lvttl one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan (a9) output output operation, test data serially loaded output via the tdo on the falling edge of tck from either the instruction register, id register and bypass register. this output is high impedance except when shifting, while in shift-dr and shift-ir controller states. tms (2) jtag mode lvttl tms is a serial input pin. one of four terminals required by ieee standard 1149.1-1990. tms directs the (b8) select input device through its tap controller states. an internal pull-up resistor forces tms high if left unconnected. trst (2) jtag reset lvttl trst is an asynchronous reset pin for the jtag controller. the jtag tap controller does not automatically (c7) input reset upon power-up, thus it must be reset by either this signal or by setting tms= high for five tck cycles. if the tap controller is not properly reset then the outputs will always be in high-impedance. if the jtag function is used but the user does not want to use trst , then trst can be tied with mrs to ensure symbol & name i/o type description pin no.
12 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits pin descriptions (continued) notes: 1. inputs should not change after master reset. 2. these pins are for the jtag port. please refer to pages 59-62 and figures 36-38. trst (2) jtag reset lvttl proper queue operation. if the jtag function is not used then this signal needs to be tied to gnd. an (continued) internal pull-up resistor forces trst high if left unconnected. waden write address hstl-lvttl the waden input is used in conjunction with wclk and the wradd address bus to select a queue to (p4) enable input be written in to. a queue addressed via the wradd bus is selected on the rising edge of wclk provided that waden is high. waden should be asserted (high) only during a queue change cycle(s). waden should not be permanently tied high. waden cannot be high for the same wclk cycle as fstr. note, that a write queue selection cannot be made, (waden must not go active) until programming of the part has been completed and seno has gone low. wclk write clock hstl-lvttl when enabled by wen , the rising edge of wclk writes data into the selected queue via the input (t7) input bus, din. the queue to be written to is selected via the wradd address bus and a rising edge of wclk while waden is high. a rising edge of wclk in conjunction with fstr and wradd will also select the flag quadrant to be placed on the paf n bus during direct flag operation. during polled flag operation the paf n bus is cycled with respect to wclk and the fsync signal is synchronized to wclk. the paf n, paf and ff outputs are all synchronized to wclk. during device expansion the fxo and fxi signals are based on wclk. the wclk must be continuous and free-running. wen write enable hstl-lvttl the wen input enables write operations to a selected queue based on a rising edge of wclk. a (t6) input queue to be written to can be selected via wclk, waden and the wradd address bus regardless of the state of wen . data present on din can be written to a newly selected queue on the second wclk cycle after queue selection provided that wen is low. a write enable is not required to cycle the paf n bus (in polled mode) or to select the paf n quadrant , (in direct mode). wradd write address hstl-lvttl for the 32q device the wradd bus is 8 bits. the wradd bus is a dual purpose address bus. the [7:0] bus input first function of wradd is to select a queue to be written to. the least significant 5 bits of the bus, (wradd7-t1 wradd[4:0] are used to address 1 of 32 possible queues within a multi-queue device. the most significant wradd6-r1 3 bits, wradd[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in wradd5-r2 expansion mode. these 3 msb?s will address a device with the matching id code. the address present wradd4-p1 on the wradd bus will be selected on a rising edge of wclk provided that waden is high, (note, that wradd3-p2 data present on the din bus can be written into the previously selected queue on this wclk edge and wradd2-p3 on the next rising wclk also, providing that wen is low). two wclk rising edges after write queue wradd1-n1 select, data can be written into the newly selected queue. wradd0-n2) the second function of the wradd bus is to select the quadrant of queues to be loaded on to the paf n bus during strobed flag mode. the least significant 2 bits, wradd[1:0] are used to select the quadrant of a device to be placed on the paf n bus. the most significant 3 bits, wradd[7:5] are again used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. address bits wradd[4:2] are don?t care during quadrant selection. the quadrant address present on the wradd bus will be selected on the rising edge of wclk provided that fstr is high, (note, that data can be written into the previously selected queue on this wclk edge). please refer to table 1 for details on the wradd bus. v cc +2.5v supply power these are v cc power supply pins and must all be connected to a +2.5v supply rail. (see pg. 13) v ddq o/p rail voltage power these pins must be tied to the desired output rail voltage. for lvttl i/o these pins must be connected (see pg. 13) to +2.5v, for hstl these pins must be connected to +1.5v and for ehstl these pins must be connected to +1.8v. gnd ground pin ground these are ground pins and must all be connected to the gnd supply rail. (see pg. 13) vref reference hstl this is a voltage reference input and must be connected to a voltage level determined from the table (k3) voltage input "recommended dc operating conditions". the input provides the reference level for hstl/ehstl inputs. for lvttl i/o mode this input should be tied to gnd. symbol & name i/o type description pin no.
13 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges pin number table symbol name i/o type pin number d[35:0] data input bus hstl-lvttl d35-j3, d( 34-32)-h(3-1), d(31-29)-g(3-1), d(28-26)-f(3-1), d(25-23)-e(3-1), d(22-20)-d(3-1), din input d(19-17)-c(3-1), d(16,15)-b(2,1), d(14-12)-a(1-3), d11-b3, d10-a4, d9-b4, d8-c4, d7-a5, d6-b5, d5-c5, d4-a6, d3-b6, d2-c6, d1-a7, d0-b7 q[35:0] data output bus hstl-lvttl q(35,34)-j(15,16), q(33-31)-h(14-16), q(30-28)-g(14-16), q(27-25)-f(14-16), q(24-22)-e(14-16), qout output q(21,20)-d(15,16), q19-b16, q(18,17)-c(16,15), q16-d14, q(15,14)-a(16,15), q13-b15, q12-a14, q11-b14, q10-c14, q9-a13, q8-b13, q7-c13, q6-a12, q5-b12, q4-c12, q3-a11, q2-b11, q(1,0)-c(11,10) v cc +2.5v supply power d(7-10), e(6,7,10,11), f(5,12), g(4,5,12,13), h(4,13), j(4,13), k(4,5,12,13), l(5,12), m(6,7,10,11), n(7-10) v ddq o/p rail voltage power d(4-6,11-13), e(4,5,12,13), f(4,13), l(4,13), m(4,5,12,13), n(4-6,11-13) gnd ground pin ground e(8-9), f(6-11), g(6-11), h(5-12), j(1,5-12), k(2,6-11,14), l(6-11), m(8-9)
14 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits symbol rating commercial unit v term terminal voltage ?0.5 to +3.6 (2) v with respect to gnd t stg storage temperature ?55 to +125 c i out dc output current ?50 to +50 ma symbol parameter min. typ. max. unit v cc supply voltage 2.375 2.5 2.625 v gnd supply voltage 0 0 0 v v ih input high voltage ? lvttl 1.7 ? 3.45 v ? ehstl v ref +0.2 ? ? v ? hstl v ref +0.2 ? ? v v il input low voltage ? lvttl -0.3 ? 0.7 v ? ehstl ? ? v ref -0.2 v ? hstl ? ? v ref -0.2 v v ref voltage reference input ? ehstl 0.8 0.9 1.0 v (hstl only) ? hstl 0.68 0.75 0.9 v t a operating temperature commercial 0 ? 70 c t a operating temperature industrial -40 ? 85 c absolute maximum ratings recommended dc operating conditions notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. compliant with jedec jesd8-5. v cc terminal only. symbol parameter (1) conditions max. unit c in (2,3) input v in = 0v 10 (3) pf capacitance c out (1,2) output v out = 0v 15 pf capacitance capacitance (t a = +25 c, f = 1.0mhz) notes: 1. with output deselected, ( oe v ih ). 2. characterized values, not currently tested. 3. c in for vref is 20pf. note: 1. v ref is only required for hstl or ehstl inputs. v ref should be tied low for lvttl operation.
15 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges dc electrical characteristics (commercial: v cc = 2.5v 0.125v, t a = 0 c to +70 c;industrial: v cc = 2.5v 0.125v, t a = -40 c to +85 c) symbol parameter min. max. unit i li input leakage current ?10 10 a i lo output leakage current ?10 10 a v oh (3) output logic ?1? voltage, i oh = ?8 ma @v ddq = 2.5v 0.125v (lvttl) v ddq -0.4 ? v i oh = ?8 ma @v ddq = 1.8v 0.1v (ehstl) v ddq -0.4 ? v i oh = ?8 ma @v ddq = 1.5v 0.1v (hstl) v ddq -0.4 ? v v ol output logic ?0? voltage, i ol = 8 ma @v ddq = 2.5v 0.125v (lvttl) ? 0.4v v i ol = 8 ma @v ddq = 1.8v 0.1v (ehstl) ? 0.4v v i ol = 8 ma @v ddq = 1.5v 0.1v (hstl) ? 0.4v v i cc1 (1,2) active v cc current (v cc = 2.5v) i/o = lvttl ? 80 ma i/o = hstl ? 150 ma i/o = ehstl ? 150 ma i cc2 (1) standby v cc current (v cc = 2.5v) i/o = lvttl ? 25 ma i/o = hstl ? 100 ma i/o = ehstl ? 100 ma i cc3 (1) standby v cc current in power down mode(v cc = 2.5v) i/o = lvttl ? ? ma i/o = hstl ? 50 ma i/o = ehstl ? 50 ma i ddq (1,2) active v ddq current (v ddq = 2.5v lvttl) i/o = lvttl ? 10 ma (v ddq = 1.5v hstl) i/o = hstl ? 10 ma (v ddq = 1.8v ehstl) i/o = ehstl ? 10 ma notes: 1. both wclk and rclk toggling at 20mhz. 2. data inputs toggling at 10mhz. 3. total power consumed: pt = [(v cc x i cc ) + (v ddq x i ddq )]. 4. outputs are not 3.3v tolerant. 5. the following inputs should be pulled to gnd: wradd, rdadd, waden, fstr, estr, sclk, si, exi, fxi and all data inputs. the following inputs should be pulled to v cc : wen , ren , seni , prs , mrs , tdi, tms and trst . all other inputs are don't care and should be at a known state.
16 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits input pulse levels 0.25 to 1.25v input rise/fall times 0.4ns input timing reference levels 0.75 output reference levels v ddq /2 hstl 1.5v ac test conditions figure 2b. lumped capacitive load, typical derating ac test loads figure 2a. ac test load input pulse levels 0.4 to 1.4v input rise/fall times 0.4ns input timing reference levels 0.9 output reference levels v ddq /2 extended hstl 1.8v ac test conditions input pulse levels gnd to 2.5v input rise/fall times 1ns input timing reference levels v cc /2 output reference levels v ddq /2 2.5v lvttl 2.5v ac test conditions 5998 drw04 50 ? v ddq /2 i/o z 0 = 50 ? 5998 drw04a 6 5 4 3 2 1 20 30 50 80 100 200 capacitance (pf) ? t cd (typical, ns) note: 1. v ddq = 1.5v. note: 1. v ddq = 1.8v. note: 1. for lvttl v cc = v ddq . output enable & disable timing v ih oe v il t oe & t olz 100mv 100mv t ohz 100mv 100mv output normally low output normally high v ol v oh v cc /2 5998 drw04b output enable output disable v cc /2 v cc /2 v cc /2 note: 1. ren is high.
17 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges advance information ac electrical characteristics (commercial: v cc = 2.5v 0.15v, t a = 0 c to +70 c;industrial: v cc = 2.5v 0.15v, t a = -40 c to +85 c; jedec jesd8-a compliant) commercial com'l & ind'l (1) IDT72T51546l5 IDT72T51546l6 idt72t51556l5 idt72t51556l6 symbol parameter min. max. min. max. unit f s clock cycle frequency (wclk & rclk) ? 200 ? 166 mhz t a data access time 0.6 3.6 0.6 3.7 ns t clk clock cycle time 5 ? 6 ? ns t clkh clock high time 2.3 ? 2.7 ? ns t clkl clock low time 2.3 ? 2.7 ? ns t ds data setup time 1.5 ? 2.0 ? ns t dh data hold time 0.5 ? 0.5 ? ns t ens enable setup time 1.5 ? 2.0 ? ns t enh enable hold time 0.5 ? 0.5 ? ns t rs reset pulse width 30 ? 30 ? ns t rss reset setup time 15 ? 15 ? ns t rsr reset recovery time 10 ? 10 ? ns t prss partial reset setup 1.5 ? 2.0 ? ns t prsh partial reset hold 0.5 ? 0.5 ? ns t olz ( oe - q n) (2) output enable to output in low-impedance 0.6 3.6 0.6 3.7 ns t ohz (2) output enable to output in high-impedance 0.6 3.6 0.6 3.7 ns t oe output enable to data output valid 0.6 3.6 0.6 3.7 ns f c clock cycle frequency (sclk) ? 10 ? 10 mhz t sclk serial clock cycle 100 ? 100 ? ns t sckh serial clock high 45 ? 45 ? ns t sckl serial clock low 45 ? 45 ? ns t sds serial data in setup 20 ? 20 ? ns t sdh serial data in hold 1.2 ? 1.2 ? ns t sens serial enable setup 20 ? 20 ? ns t senh serial enable hold 1.2 ? 1.2 ? ns t sdo sclk to serial data out ? 20 ? 20 ns t seno sclk to serial enable out ? 20 ? 20 ns t sdop serial data out propagation delay 1.5 3.7 1.5 3.7 ns t senop serial enable propagation delay 1.5 3.7 1.5 3.7 ns t pcwq programming complete to write queue selection 20 ? 20 ? ns t pcrq programming complete to read queue selection 20 ? 20 ? ns t as address setup 1.5 ? 2.5 ? ns t ah address hold 1.0 ? 1.5 ? ns t wff write clock to full flag ? 3.6 ? 3.7 ns t rov read clock to output valid ? 3.6 ? 3.7 ns t sts pae / paf strobe setup 1.5 ? 2.0 ? ns t sth pae / paf strobe hold 0.5 ? 0.5 ? ns t qs queue setup 1.5 ? 2.0 ? ns t qh queue hold 1.0 ? 0.5 ? ns t waf wclk to paf flag 0.6 3.6 0.6 3.7 ns t rae rclk to pae flag 0.6 3.6 0.6 3.7 ns t paf write clock to synchronous almost-full flag bus 0.6 3.6 0.6 3.7 ns t pae read clock to synchronous almost-empty flag bus 0.6 3.6 0.6 3.7 ns notes: 1. industrial temperature range product for the 6ns is available as a standard device. all other speed grades available by spec ial order. 2. values guaranteed by design, not currently tested.
18 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits advance information ac electrical characteristics (continued) (commercial: v cc = 2.5v 0.15v, t a = 0 c to +70 c;industrial: v cc = 2.5v 0.15v, t a = -40 c to +85 c; jedec jesd8-a compliant) t erclk rclk to echo rclk output ? 4.0 ? 4.2 ns t clken rclk to echo ren output ? 3.6 ? 3.7 ns t paelz (2) rclk to pae flag bus to low-impedance 0.6 3.6 0.6 3.7 ns t paehz (2) rclk to pae flag bus to high-impedance 0.6 3.6 0.6 3.7 ns t paflz (2) wclk to paf flag bus to low-impedance 0.6 3.6 0.6 3.7 ns t pafhz (2) wclk to paf flag bus to high-impedance 0.6 3.6 0.6 3.7 ns t ffhz (2) wclk to full flag to high-impedance 0.6 3.6 0.6 3.7 ns t fflz (2) wclk to full flag to low-impedance 0.6 3.6 0.6 3.7 ns t ovlz (2) rclk to output valid flag to low-impedance 0.6 3.6 0.6 3.7 ns t ovhz (2) rclk to output valid flag to high-impedance 0.6 3.6 0.6 3.7 ns t fsync wclk to paf bus sync to output 0.6 3.6 0.6 3.7 ns t fxo wclk to paf bus expansion to output 0.6 3.6 0.6 3.7 ns t esync rclk to pae bus sync to output 0.6 3.6 0.6 3.7 ns t exo rclk to pae bus expansion to output 0.6 3.6 0.6 3.7 ns t pr rclk to packet ready flag 0.6 3.6 0.6 3.7 ns t skew1 skew time between rclk and wclk for ff and ov 4 ? 4.5 ? ns t skew2 skew time between rclk and wclk for paf and pae 5? 6?ns t skew3 skew time between rclk and wclk for paf [0:7] and pae [0:7] 5 ? 6 ? ns t skew4 skew time between rclk and wclk for pr and ov 5? 6?ns t skew5 skew time between rclk and wclk for ov when in packet mode 8 ? 10 ? ns t xis expansion input setup 1.0 ? 1.0 ? ns t xih expansion input hold 0.5 ? 0.5 ? ns commercial com'l & ind'l (1) IDT72T51546l5 IDT72T51546l6 idt72t51556l5 idt72t51556l6 symbol parameter min. max. min. max. unit notes: 1. industrial temperature range product for the 6ns is available as a standard device. all other speed grades available by spec ial order. 2. values guaranteed by design, not currently tested.
19 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges functional description master reset a master reset is performed by toggling the mrs input from high to low to high. during a master reset all internal multi-queue device setup and control registers are initialized and require programming either serially by the user via the serial port, or using the default settings. during a master reset the state of the following inputs determine the functionality of the part, these pins should be held high or low. pkt ? packet mode fm ? flag bus mode iw, ow, bm ? bus matching options mast ? master device id0, 1, 2 ? device id dfm ? programming mode, serial or default df ? offset value for pae and paf once a master reset has taken place, the device must be programmed either serially or via the default method before any read/write operations can begin. see figure 5, master reset for relevant timing. partial reset a partial reset is a means by which the user can reset both the read and write pointers of a single queue that has been setup within a multi-queue device. before a partial reset can take place on a queue, the respective queue must be selected on both the read port and write port a minimum of 2 rclk and 2 wclk cycles before the prs goes low. the partial reset is then performed by toggling the prs input from high to low to high, maintaining the low state for at least one wclk and one rclk cycle. once a partial reset has taken place a minimum of 3 wclk and 3 rclk cycles must occur before enabled writes or reads can occur. a partial reset only resets the read and write pointers of a given queue, a partial reset will not effect the overall configuration and setup of the multi-queue device and its queues. see figure 6, partial reset for relevant timing. serial programming the multi-queue flow-control device is a fully programmable device, provid- ing the user with flexibility in how queues are configured in terms of the number of queues, depth of each queue and position of the paf / pae flags within respective queues. all user programming is done via the serial port after a master reset has taken place. internally the multi-queue device has setup registers which must be serially loaded, these registers contain values for every queue within the device, such as the depth and pae / paf offset values. the IDT72T51546/72t51556 devices are capable of up to 32 queues and therefore contain 32 sets of registers for the setup of each queue. during a master reset if the dfm (default mode) input is low, then the device will require serial programming by the user. it is recommended that the user utilize a ?c? program provided by idt, this program will prompt the user for all information regarding the multi-queue setup. the program will then generate a serial bit stream which should be serially loaded into the device via the serial port. for the IDT72T51546/72t51556 devices the serial programming re- quires a total number of serially loaded bits per device, (sclk cycles with seni enabled), calculated by: 19+(qx72) where q is the number of queues the user wishes to setup within the device. once the master reset is complete and mrs is high, the device can be serially loaded. data present on the si (serial in), input is loaded into the serial port on a rising edge of sclk (serial clock), provided that seni (serial in enable), is low. once serial programming of the device has been successfully completed the device will indicate this via the seno (serial output enable) going active, low. upon detection of completion of programming, the user should cease all programming and take seni inactive, high. note, seno follows seni once programming of a device is complete. therefore, seno will go low after programming provided seni is low, once seni is taken high again, seno will also go high. the operation of the so output is similar, when programming of a given device is complete, the so output will follow the si input. if devices are being used in expansion mode the serial ports of devices should be cascaded. the user can load all devices via the serial input port control pins, si & seni , of the first device in the chain. again, the user may utilize the ?c? program to generate the serial bit stream, the program prompting the user for the number of devices to be programmed. the seno and so (serial out) of the first device should be connected to the seni and si inputs of the second device respectively and so on, with the seno & so outputs connecting to the seni & si inputs of all devices through the chain. all devices in the chain should be connected to a common sclk. the serial output port of the final device should be monitored by the user. when seno of the final device goes low, this indicates that serial programming of all devices has been successfully com- pleted. upon detection of completion of programming, the user should cease all programming and take seni of the first device in the chain inactive, high. as mentioned, the first device in the chain has its serial input port controlled by the user, this is the first device to have its internal registers serially loaded by the serial bit stream. when programming of this device is complete it will take its seno output low and bypass the serial data loaded on the si input to its so output. the serial input of the second device in the chain is now loaded with the data from the so of the first device, while the second device has its seni input low. this process continues through the chain until all devices are programmed and the seno of the final device goes low. once all serial programming has been successfully completed, normal operations, (queue selections on the read and write ports) may begin. when connected in expansion mode, the IDT72T51546/72t51556 devices require a total number of serially loaded bits per device to complete serial programming, (sclk cycles with seni enabled), calculated by: n[19+(qx72)] where q is the number of queues the user wishes to setup within the device, where n is the number of devices in the chain. see figure 7, serial port connection and figure 8, serial programming for connection and timing information. default programming during a master reset if the dfm (default mode) input is high the multi- queue device will be configured for default programming, (serial programming is not permitted). default programming provides the user with a simpler, however limited means by which to setup the multi-queue flow-control device, rather than using the serial programming method. the default mode will configure a multi-queue device such that the maximum number of queues possible are setup, with all of the parts available memory blocks being allocated equally between the queues. the values of the pae / paf offsets is determined by the state of the df (default) pin during a master reset. for the IDT72T51546/72t51556 devices the default mode will setup 32 queues, each queue being 1024 x36 and 2048 x36 deep respectively. for both devices the value of the pae / paf offsets is determined at master reset by the state of the df input. if df is low then both the pae & paf offset will be 8, if high then the value is 128. when configuring the IDT72T51546/72t51556 devices in default mode the user simply has to apply wclk cycles after a master reset, until seno goes low, this signals that default programming is complete. these clock cycles are required for the device to load its internal setup registers. when a single multi- queue device is used, the completion of device programming is signaled by the
20 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits seno output of a device going from high to low. note, that seni must be held low when a device is setup for default programming mode. when multi-queue devices are connected in expansion mode, the seni of the first device in a chain can be held low. the seno of a device should connect to the seni of the next device in the chain. the seno of the final device is used to indicate that default programming of all devices is complete. when the final seno goes low normal operations may begin. again, all devices will be programmed with their maximum number of queues and the memory divided equally between them. please refer to figure 9, default programming . reading and writing to the idt multi-queue flow-control device the IDT72T51546/72t51556 multi-queue flow-control devices can be configured in two distinct modes, namely standard mode and packet mode. standard mode operation (pkt = low on master reset) write queue selection and write operation (standard mode) the IDT72T51546/72t51556 multi-queue flow-control devices can be configured up to a maximum of 32 queues into which data can be written via a common write port using the data inputs (din), write clock (wclk) and write enable ( wen ). the queue to be written is selected by the address present on the write address bus (wradd) during a rising edge on wclk while write address enable (waden) is high. the state of wen does not impact the queue selection. the queue selection requires 1 wclk cycle. all subsequent data writes will be to this queue until another queue is selected. standard mode operation is defined as individual words will be written to the device as opposed to packet mode where complete packets may be written. the write port is designed such that 100% bus utilization can be obtained. this means that data can be written into the device on every wclk rising edge including the cycle that a new queue is being addressed. changing queues requires a minimum of 3 wclk cycles on the write port (see figure 10, write queue select, write operation and full flag operation ). waden goes high signaling a change of queue (clock cycle ?a?). the address on wradd at that time determines the next queue. data presented during that cycle (?a?) and the next cycle (?b? and ?c?), will be written to the active (old) queue, provided wen is active low. if wen is high (inactive) for these 3 clock cycles, data will not be written in to the previous queue. the write port discrete full flag will update to show the full status of the newly selected queue (q x ) at this last cycle?s rising edge (?c?). data present on the data input bus (din), can be written into the newly selected queue (q x ) on the rising edge of wclk on the third cycle (?d?) following a change of queue, provided wen is low and the new queue is not full. if the newly selected queue is full at the point of its selection, any writes to that queue will be prevented. data cannot be written into a full queue. refer to figure 10, write queue select, write operation and full flag operation , figure 11, write operations & first word fall through for timing diagrams and figure 12, full flag timing in expansion mode for timing diagrams. table 1 write address bus, wradd[7:0] operation wclk waden fstr wradd[7:0] write queue select 10 01 device select (compared to id0,1,2) write queue address (5 bits = 32 queues) 765 432 10 765 432 10 device select (compared to id0,1,2) x x x quadrant address paf n quadrant select q0 : q7 paf 0 : paf 7 quadrant address queue status on paf n bus 00 01 10 11 q8 : q15 paf 0 : paf 7 q16 : q23 paf 0 : paf 7 q24 : q31 paf 0 : paf 7 5998 drw05
21 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges read queue selection and read operation (standard mode) the IDT72T51546/72t51556 multi-queue flow-control devices can be configured up to a maximum of 32 queues which data can be read via a common read port using the data outputs (qout), read clock (rclk) and read enable ( ren ). an output enable, oe control pin is also provided to allow high- impedance selection of the qout data outputs. the multi-queue device read port operates in a mode similar to ?first word fall through? on a supersync idt fifo, but with the added feature of data output pipelining (see figure 11, write operations & first word fall through ). the queue to be read is selected by the address presented on the read address bus (rdadd) during a rising edge on rclk while read address enable (raden) is high. the state of ren does not impact the queue selection. the queue selection requires 1 rclk cycles. all subsequent data reads will be from this queue until another queue is selected. standard mode operation is defined as individual words will be read from the device as opposed to packet mode where complete packets may be read. the read port is designed such that 100% bus utilization can be obtained. this means that data can be read out of the device on every rclk rising edge including the cycle that a new queue is being addressed. changing queues requires a minimum of three rclk cycles on the read port (see figure 13, read queue select, read operation ). raden goes high signaling a change of queue (clock cycle ?d?). the address on rdadd at that time determines the next queue. data presented during that cycle (?d?) will be read at ?d? (+ t a ), and the next cycle (?e?), can continue to be read from the active (old) queue (q p ), provided ren is active low. if ren is high (inactive) for these two clock cycles, data will not be read from the previous queue. the next cycle?s rising edge (?f?), the read port discrete empty flag will update to show the empty status of the newly selected queue (q f ). the internal pipeline is also loaded at this time (?f?) with the last word from the previous (old) queue (q f ) as well as the next word from the new queue (q f ). both of these words will fall through to the output register (provided the oe is asserted) consecutively (cycles ?f? and ?g? respectively) following the selection of the new queue regardless of the state of ren , unless the new queue (q f ) is empty. if the newly selected queue is empty, any reads from that queue will be prevented. data cannot be read from an empty queue. the last word in the data output register (from the previous queue), will remain on the data bus, but the output valid flag, ov will go high, to indicate that the data present is no longer valid. this pipelining effect provides the user with 100% bus utilization, and brings about the possibility that a ?null? queue may be required within a multi-queue device. null queue operation is discussed in the next section. remember that oe allows the user to place the data output bus (qout) into high-impedance and the data can be read in to the output register regardless of oe . refer to table 2, for read address bus arrangement. also, refer to figures 13, 15, and 16 for read queue selection and read port operation timing diagrams. packet mode operation (pkt = high on master reset) the packet mode operation provides the capability where, user defined packets or frames can be written to the device as opposed to standard mode where individual words are written. for clarification, in packet mode, a packet can be written to the device with the starting location designated as transmit start of packet (tsop) and the ending location designated as transmit end of packet (teop). in conjunction, a packet read from the device will be designated as operation rclk raden estr rdadd[7:0] read queue select 10 01 device select (compared to id0,1,2) read queue address (5 bits = 32 queues) 765 432 10 765 432 10 device select (compared to id0,1,2) x x x quadrant address pae n/ pr n quadrant select q0 : q7 pae 0 : pae 7 quadrant address queue status on pae n/ pr n bus 00 01 10 11 q8 : q15 pae 0 : pae 7 q16 : q23 pae 0 : pae 7 q24 : q31 pae 0 : pae 7 5998 drw06 null-q 0 0 10 765 432 10 xxx null queue select 1 xx xxx table 2 read address bus, rdadd[7:0]
22 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits receive start of packet (rsop) and a receive end of packet (reop). the minimum size for a packet is four words (sop, two words of data and eop). the almost empty flag bus becomes the ?packet ready? pr flag bus when the device is configured for packet mode. valid packets are indicated when both pr and ov are asserted. write queue selection and write operation (packet mode) it is required that a full packet be written to a queue before moving to a different queue. the device requires three cycles to change queues. packet mode, has 2 restrictions: <1> an extra word (or filler word) is required to be written after each packet on the cycle following the queue change to ensure the rsop in the old queue is not read out on a queue change because of the first word fall through. <2> no sop/eop is allowed to read/written at cycle (?d? or ?k?) the second cycle after a queue change. in this mode, the write port may not obtain 100% bus utilization. changing queues requires a minimum of 3 wclk cycles on the write port (see figure 17, writing in packet mode during a queue change ). waden goes high signaling a change of queue (clock cycle ?b? or ?i?). the address on wradd at the rising edge of wclk determines the next queue. data presented on din during that cycle (?b? or ?i?) and the next cycle (?c? or ?j?) can continue to be written to the active (old) queue (q a or q b respectively), provided wen is low (active). if wen is high (inactive) for these two clock cycles (h), data will not be written in to the previous queue (q a ). the second cycle following a request for queue change (?d? or ?k?) will require a ?filler? word to be written to the device. this can be done by clocking the teop twice or by writing a ?filler? word. in packet mode, the multi-queue is designed under the 2 restrictions listed previously. note, an erroneous packet ready flag may occur if the eop or sop marker shows up at the second cycle after a queue change. to prevent an erroneous packet ready flag from occurring a filler word should be written into the old queue at the last clock cycle of writing. it is important to know that no sop or eop may be written into the device during this cycle (?d? or ?k?). the write port discrete full flag will update to show the full status of the newly selected queue (q b ) at this last cycle?s rising edge (?d? or ?k?). data values presented on the data input bus (din), can be written into the newly selected queue (q x ) on the rising edge of wclk on the third cycle (?e?) following a request for change of queue, provided wen is low (active) and the new queue is not full. if a selected queue is full ( ff is low), then writes to that queue will be prevented. note, data cannot be written into a full queue. refer to figure 17, writing in packet mode during a queue change and figure 19, data input (transit) packet mode of operation for timing diagrams. read queue selection and read operation (packet mode) in packet mode it is required that a full packet is read from a queue before moving to a different queue. the device requires three cycles to change queues. in packet mode, there are 2 restrictions <1> an extra word (or filler word) should have been inserted into the data stream after each packet to insure the rsop in the old queue is not read out on a queue change because of the first word fall through and this word should be discarded. <2> no eop/sop is allowed to be read/written at cycle (?d? or ?k?) the second cycle after a queue change). in this mode, the read port may not obtain 100% bus utilization. changing queues requires a minimum of 3 rclk cycles on the read port (see figure 18, reading in packet mode during a queue change ). raden goes high signaling a change of queue (clock cycle ?b? or ?i?). the address on rdadd at the rising edge of rclk determines the queue. as illustrated in figure 18 during cycle (?b? or ?i?), and the next cycle (?c? or ?j?) data can continue to be read from the active (old) queue (q a or q b respectively), provided both ren and oe are low (active) simultaneously with changing queues. reop for packet located in queue (q a ) must be read on or before a queue change request is made (?c? or ?j?). if ren is high (inactive) for these two clock cycles, data will not be read from the previous queue (q a ). in applications where the multi-queue flow-control device is connected to a shared bus, an output enable, oe control pin is also provided to allow high-impedance selection of the data outputs (qout). with reference to figure 18 when changing queues, a packet marker (sop or eop) should not be read on cycle (?e? or ?l?). reading a sop or eop should not occur during the cycles required for a queue change. it is also recommended that a queue change should not occur once the reading of the packet has commenced, the eop marker of the packet prior to a queue change should be read on or before the queue change. if the eop word is read before a queue change, ren can be pulled high to disable further reads. when the queue change is initiated, the filler word written into the current queue after the eop word will fall through followed by and the first word from the new queue. refer to figure 18, reading in packet mode during a queue change as well as figures 13, 15, and 16 for timing diagrams and table 2, for read address bus arrangement. note, the almost empty flag bus becomes the ?packet ready? flag bus when the device is configured for packet ready mode. . packet ready flag the 36-bit multi-queue flow-control device provides the user with a packet ready feature. during a master reset the logic ?1? (high) on the pkt input signal (packet mode select), configures the device in packet mode. the pr discrete flag, provides a packet ready status of the active queue selected on the read port. a packet ready status is individually maintained on all queues; however only the queue selected on the read port has its packet ready status indicated on the pr output flag. a packet is available on the output for reading when both pr and ov are asserted low. if less than a full packet is available, the pr flag will be high (packet not ready). in packet mode, no words can be read from a queue until a complete packet has been written into that queue, regardless of ren . when packet mode is selected the programmable almost empty bus, pae n, becomes the packet ready bus, pr n. when configured in direct bus (fm = low during a master reset), the pr n bus provides packet ready status in 8 queue increments. the pr n bus supports either polled or direct modes of operation. the pr n mode of operation is configured through the flag mode (fm) bit during a master reset. when the multi-queue is configured for packet mode operation, the device must also be configured for 36 bit write data bus and 36 bit read data bus. the two most significant bits of the 36-bit data bus are used as ?packet markers?. on the write port these are bits d34 (transmit start of packet,) d35 (transmit end of packet) and on the read port q34, q35. all four bits are monitored by the packet control logic as data is written into and read out from the queues. the packet ready status for individual queues is then determined by the packet ready logic. on the write port d34 is used to ?mark? the first word being written into the selected queue as the ?transmit start of packet?, tsop. to further clarify, when the user requires a word being written to be marked as the start of a packet, the tsop input (d34) must be high for the same wclk rising edge as the word that is written. the tsop marker is stored in the queue along with the data it was written in until the word is read out of the queue via the read port. on the write port d35 is used to ?mark? the last word of the packet currently being written into the selected queue as the ?transmit end of packet? teop. when the user requires a word being written to be marked as the end of a packet, the teop input must be high for the same wclk rising edge as the word that is written in. the teop marker is stored in the queue along with the data it was written in until the word is read out of the queue via the read port. the packet ready logic monitors all start and end of packet markers both as they enter respective queues via the write port and as they exit queues via the
23 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges read port. the multi-queue internal logic increments and decrements a packet counter, which is provided for each queue. the functionality of the packet ready logic provides status as to whether at least one full packet of data is available within the selected queue. a partial packet in a queue is regarded as a packet not ready and pr (active low) will be high. in packet mode, no words can be read from a queue until at least one complete packet has been written into the queue, regardless of ren . for example, if a tsop has been written and some number of words later a teop is written a full packet of data is deemed to be available, and the pr flag and ov will go active low. consequently if reads begin from a queue that has only one complete packet and the rsop is detected on the output port as data is being read out, pr will go inactive high. ov will remain low indicating there is still valid data being read out of that queue until the reop is read. the user may proceed with the reading operation until the current packet has been read out and no further complete packets are available. if during that time another complete packet has been written into the queue and the pr flag will again gone active, then reads from the new packet may follow after the current packet has been completely read out. the packet counters therefore look for start of packet markers followed by end of packet markers and regard data in between the tsop and teop as a full packet of data. the packet monitoring has no limitation as to how many packets are written into a queue, the only constraint is the depth of the queue. note, there is a minimum allowable packet size of four words, inclusive of the tsop marker and teop marker. the packet logic does expect a tsop marker to be followed by a teop marker. if a second tsop marker is written after a first, it is ignored and the logic regards data between the first tsop and the first subsequent teop as the full packet. the same is true for teop; a second consecutive teop mark is ignored. on the read side the user should regard a packet as being between the first rsop and the first subsequent reop and disregard consecutive rsop markers and/or reop markers. this is why a teop may be written twice, using the second teop as the ?filler? word. as an example, the user may also wish to implement the use of an ?almost end of packet? (aeop) marker. for example, the aeop can be assigned to data input bit d33. the purpose of this aeop marker is to provide an indicator that the end of packet is a fixed (known) number of reads away from the end of packet. this is a useful feature when due to latencies within the system, monitoring the reop marker alone does not prevent ?over reading? of the data from the queue selected. for example, an aeop marker set 4 writes before the teop marker provides the device connected to the read port with and ?almost end of packet? indication 4 cycles before the end of packet. the aeop can be set any number of words before the end of packet determined by user requirements or latencies involved in the system. see figure 18, reading in packet mode during a queue change , figure 19, data input (transmit) packet mode of operation and figure 20, data output (receive) packet mode of operation . packet mode ? modulo operation the internal packet ready control logic performs no operation on these modulo bits, they are only informational bits that are passed through with the respective data byte(s). when utilizing the multi-queue flow-control device in packet mode, the user may also want to consider the implementation of ?modulo? operation or ?valid byte marking?. modulo operation may be useful when the packets being transferred through a queue are in a specific byte arrangement even though the data bus width is 36 bits. in modulo operation the user can concatenate bytes to form a specific data string through the multi-queue device. a possible scenario is where a limited number of bytes are extracted from the packet for either analysis or filtered for security protection. this will only occur when the first 36 bit word of a packet is written in and the last 36 bit word of packet is written in. the modulo operation is a means by which the user can mark and identify specific data within the queue. on the write port data input bits, d32 (transmit modulo bit 2, tmod2) and d33 (transmit modulo bit 1, tmod1) can be used as data markers. an example of this could be to use d32 and d33 to code which bytes of a word are part of the packet that is also being marked as the ?start of marker? or ?end of marker?. conversely on the read port when reading out these marked words, data outputs q32 (receive modulo bit 2, rmod2) and q33 (receive modulo bit 1, rmod1) will pass on the byte validity information for that word. refer to table 5 for one example of how the modulo bits may be setup and used. see figure 19, data input (transmit) packet mode of operation and figure 20, data output (receive) packet mode of operation . byte a byte b byte c byte d d0/q0 d35/q35 tmod1 (d33) rmod1 (q33) tmod2 (d32) rmod2 (q32) valid bytes 0 0 a, b, c, d 01a 1 0 a, b 1 1 a, b, c d15/q15 d23/q23 d31/q31 d34/q34 d33/q33 d32/q32 mod 2 mod 1 sop eop d7/q7 5998 drw07 note: packet mode is only available when the input port and output port are 36 bits wide. table 5 packet mode valid byte
24 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits null queue operation (of the read port) pipelining of data to the output port enables the device to provide 100% bus utilization in standard mode. data can be read out of the multi-queue flow-control device on every rclk cycle regardless of queue switches or other operations. the device architecture is such that the pipeline is constantly filled with the next words in a selected queue to be read out, again providing 100% bus utilization. this type of architecture does assume that the user is constantly switching queues such that during a queue switch, the last data word required from the previous queue will fall through the pipeline to the output. note, that if reads cease at the empty boundary of a queue, then the last word will automatically flow through the pipeline to the output. the null q operation is achieved by setting the null q signal high during a queue select. note that the read address bus rdadd[7:0] is a don't care. the null queue is a separate queue within the device and thus the maximum number of queues and memory is always available regardless of whether or not the null queue is used. also note that in expansion mode a user may want to use a dedicated null queue for each device. a null queue can be selected when no further reads are required from a previously selected queue. changing to a null queue will continue to propagate data in the pipeline to the previous queue's output. the null q can remain selected until a data becomes available in another queue for reading. the null-q can be utilized in either standard or packet mode. note: if the user switches the read port to the null queue, this queue is seen as and treated as an empty queue, therefore after switching to the null queue the last word from the previous queue will remain in the output register and the ov flag will go high, indicating data is not valid. the null queue operation only has significance to the read port of the multi- queue, it is a means to force data through the pipeline to the output. null q selection and operation has no meaning on the write port of the device. also, refer to figure 21, read operation and null queue select for diagram. paf n flag bus operation the IDT72T51546/72t51556 multi-queue flow-control device can be configured for up to 32 queues, each queue having its own almost full status. an active queue has its flag status output to the discrete flags, ff and paf , on the write port. queues that are not selected for a write operation can have their paf status monitored via the paf n bus. the paf n flag bus is 8 bits wide, so that 8 queues at a time can have their status output to the bus. if 9 or more queues are setup within a device then there are 2 methods by which the device can share the bus between queues, ?direct? mode and ?polled? mode depending on the state of the fm (flag mode) input during a master reset. if 8 or less queues are setup within a device then each will have its own dedicated output from the bus. if 8 or less queues are setup in single device mode, it is recommended to configure the paf n bus to polled mode as it does not require using the write address (wradd). expanding up to 256 queues or providing deeper queues expansion can take place using either the standard mode or the packet mode. in the 32 queue multi-queue device, the wradd address bus is 8 bits wide. the 5 least significant bits (lsbs) are used to address one of the 32 available queues within a single multi-queue device. the 3 most significant bits (msbs) are used when a device is connected in expansion mode with up to 8 devices connected in width expansion, each device having its own 3-bit address. when logically expanded with multiple parts, each device is statically setup with a unique chip id code on the id pins, id0, id1, and id2. a device is selected when the 3 most significant bits of the wradd address bus matches a 3-bit id code. the maximum logical expansion is 256 queues (32 queues x 8 devices) or a minimum of 8 queues (1 queue per device x 8 devices), each of the maximum size of the individual memory device. note: the wradd bus is also used in conjunction with fstr (almost full flag bus strobe), to address the almost full flag bus during direct mode of operation. refer to table 1, for write address bus arrangement. also, refer to figure 12, full flag timing expansion mode , figure 14, output valid flag timing (in expansion mode) , and figure 35, multi-queue expansion diagram , for timing diagrams. bus matching operation bus matching operation between the input port and output port is available. during a master reset of the multi-queue the state of the three setup pins, bm (bus matching), iw (input width) and ow (output width) determine the input and output port bus widths as per the selections shown in table 3, ?bus matching set-up?. 9 bit bytes, 18 bit words and 36 bit long words can be written into and read from the queues provided that at least one of the ports is setup for x36 operation. when writing to or reading from the multi-queue in a bus matching mode, the device orders data in a ?little endian? format. see figure 4, bus matching byte arrangement for details. the full flag and almost full flag operation is always based on writes and reads of data widths determined by the write port width. for example, if the input port is x36 and the output port is x9, then four data reads from a full queue will be required to cause the full flag to go high (queue not full). conversely, the output valid flag and almost empty flag operations are always based on writes and reads of data widths determined by the read port. for example, if the input port is x18 and the output port is x36, two write operations will be required to cause the output valid flag of an empty queue to go low, output valid (queue is not empty). note, that the input port serves all queues within a device, as does the output port, therefore the input bus width to all queues is equal (determined by the input port size) and the output bus width from all queues is equal (determined by the output port size). bm i w ow write port read port 0 x x x36 x36 1 0 0 x36 x18 1 0 1 x36 x9 1 1 0 x18 x36 1 1 1 x9 x36 x36 device table 3 bus-matching set-up full flag operation the multi-queue flow-control device provides a single full flag output, ff . the ff flag output provides a full status of the queue currently selected on the write port for write operations. internally the multi-queue flow-control device monitors and maintains a status of the full condition of all queues within it, however only the queue that is selected for write operations has its full status output to the ff flag. this dedicated flag is often referred to as the ?active queue full flag?. when queue switches are being made on the write port, the ff flag output will switch to the new queue and provide the user with the new queue status, on the cycle after a new queue selection is made. the user then has a full status for the new queue one cycle ahead of the wclk rising edge that data can be written into the new queue. that is, a new queue can be selected on the write port via the wradd bus, waden enable and a rising edge of wclk. on the second rising edge of wclk, the ff flag output will show the full status of the newly selected queue. on the third rising edge of wclk following the queue selection, data can be written into the newly selected queue provided that data and enable setup & hold times are met.
25 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges note, the ff flag will provide status of a newly selected queue two wclk cycle after queue selection, which is one cycle before data can be written to that queue. this prevents the user from writing data to a queue that is full, (assuming that a queue switch has been made to a queue that is actually full). the ff flag is synchronous to the wclk and all transitions of the ff flag occur based on a rising edge of wclk. internally the multi-queue device monitors and keeps a record of the full status for all queues. it is possible that the status of a ff flag maybe changing internally even though that flag is not the active queue flag (selected on the write port). a queue selected on the read port may experience a change of its internal full flag status based on read operations. see figure 10, write queue select, write operation and full flag operation and figure 12, full flag timing in expansion mode for timing information. expansion mode - full flag operation when multi-queue devices are connected in expansion mode the ff flags of all devices should be connected together, such that a system controller monitoring and managing the multi-queue devices write port only looks at a single ff flag (as opposed to a discrete ff flag for each device). this ff flag is only pertinent to the queue being selected for write operations at that time. remember, that when in expansion mode only one multi-queue device can be written to at any moment in time, thus the ff flag provides status of the active queue on the write port. this connection of flag outputs to create a single flag requires that the ff flag output have a high-impedance capability, such that when a queue selection is made only a single device drives the ff flag bus and all other ff flag outputs connected to the ff flag bus are placed into high-impedance. the user does not have to select this high-impedance state, a given multi-queue flow-control device will automatically place its ff flag output into high-impedance when none of its queues are selected for write operations. when queues within a single device are selected for write operations, the ff flag output of that device will maintain control of the ff flag b us. its ff flag will simply update between queue switches to show the respective queue full status. the multi-queue device places its ff flag output into high-impedance based on the 3 bit id code found in the 3 most significant bits of the write queue address bus, wradd. if the 3 most significant bits of wradd match the 3 bit id code setup on the static inputs, id0, id1 and id2 then the ff flag output of the respective device will be in a low-impedance state. if they do not match, then the ff flag output of the respective device will be in a high-impedance state. see figure 12, full flag timing in expansion mode for details of flag operation, including when more than one device is connected in expansion. output valid flag operation the multi-queue flow-control device provides a single output valid flag output, ov . the ov provides an empty status or data output valid status for the data word currently available on the output register of the read port. the rising edge of an rclk cycle that places new data onto the output register of the read port, also updates the ov flag to show whether or not that new data word is actually valid. internally the multi-queue flow-control device monitors and maintains a status of the empty condition of all queues within it, however only the queue that is selected for read operations has its output valid (empty) status output to the ov flag, giving a valid status for the word being read at that time. the nature of the first word fall through operation means that when the last data word is read from a selected queue, the ov flag will go high on the next enabled read, that is, on the next rising edge of rclk while ren is low. when queue switches are being made on the read port, the ov flag will switch to show status of the new queue in line with the data output from the new queue. when a queue selection is made the first data from that queue will appear on the qout data outputs 3 rclk cycles later, the ov will change state to indicate validity of the data from the newly selected queue on this 3 rd rclk cycle also. the previous cycles will continue to output data from the previous queue and the ov flag will indicate the status of those outputs. again, the ov flag always indicates status for the data currently present on the output register. the ov flag is synchronous to the rclk and all transitions of the ov flag occur based on a rising edge of rclk. internally the multi-queue device monitors and keeps a record of the output valid (empty) status for all queues. it is possible that the status of an ov flag may be changing internally even though that respective flag is not the active queue flag (selected on the read port). a queue selected on the write port may experience a change of its internal ov flag status based on write operations, that is, data may be written into that queue causing it to become ?not empty?. see figure 13, read queue select, read operation and figure 14, output valid flag timing for details of the timing. expansion mode ? output valid flag operation when multi-queue devices are connected in expansion mode, the ov flags of all devices should be connected together, such that a system controller monitoring and managing the multi-queue devices read port only looks at a single ov flag (as opposed to a discrete ov flag for each device). this ov flag is only pertinent to the queue being selected for read operations at that time. remember, that when in expansion mode only one multi-queue device can be read from at any moment in time, thus the ov flag provides status of the active queue on the read port. this connection of flag outputs to create a single flag requires that the ov flag output have a high-impedance capability, such that when a queue selection is made only a single device drives the ov flag bus and all other ov flag outputs connected to the ov flag bus are placed into high-impedance. the user does not have to select this high-impedance state, a given multi-queue flow-control device will automatically place its ov flag output into high-impedance when none of its queues are selected for read operations. when queues within a single device are selected for read operations, the ov flag output of that device will maintain control of the ov flag bus. its ov flag will simply update between queue switches to show the respective queue output valid status. the multi-queue device places its ov flag output into high-impedance based on the 3 bit id code found in the 3 most significant bits of the read queue address bus, rdadd. if the 3 most significant bits of rdadd match the 3 bit id code setup on the static inputs, id0, id1 and id2 then the ov flag output of the respective device will be in a low-impedance state. if they do not match, then the ov flag output of the respective device will be in a high-impedance state. see figure 14, output valid flag timing for details of flag operation, including when more than one device is connected in expansion. almost full flag as previously mentioned the multi-queue flow-control device provides a single programmable almost full flag output, paf . the paf flag output provides a status of the almost full condition for the active queue currently selected on the write port for write operations. internally the multi-queue flow-control device monitors and maintains a status of the almost full condition of all queues within it, however only the queue that is selected for write operations has its full status output to the paf flag. this dedicated flag is often referred to as the ?active queue almost full flag?. the position of the paf flag boundary within a queue can be at any point within that queues depth. this location can be user programmed via the serial port or one of the default values (8 or 128) can be selected if the user has performed default programming.
26 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits as mentioned, every queue within a multi-queue device has its own almost full status, when a queue is selected on the write port, this status is output via the paf flag. the paf flag value for each queue is programmed during multi-queue device programming (along with the number of queues, queue depths and almost empty values). the paf offset value, m, for a respective queue can be programmed to be anywhere between ?0? and ?d?, where ?d? is the total memory depth for that queue. the paf value of different queues within the same device can be different values. when queue switches are being made on the write port, the paf flag output will switch to the new queue and provide the user with the new queue status, on the third cycle after a new queue selection is made, on the same wclk cycle that data can actually be written to the new queue. that is, a new queue can be selected on the write port via the wradd bus, waden enable and a rising edge of wclk. on the third rising edge of wclk following a queue selection, the paf flag output will show the full status of the newly selected queue. the paf is flag output is triple register buffered, so when a write operation occurs at the almost full boundary causing the selected queue status to go almost full the paf will go low 3 wclk cycles after the write. the same is true when a read occurs, there will be a 3 wclk cycle delay after the read operation. so the paf flag delays are: from a write operation to paf flag low is 2 wclk + t waf the delay from a read operation to paf flag high is t skew2 + wclk + t waf note, if t skew is violated there will be one added wclk cycle delay. the paf flag is synchronous to the wclk and all transitions of the paf flag occur based on a rising edge of wclk. internally the multi-queue device monitors and keeps a record of the almost full status for all queues. it is possible that the status of a paf flag maybe changing internally even though that flag is not the active queue flag (selected on the write port). a queue selected on the read port may experience a change of its internal almost full flag status based on read operations. the multi-queue flow-control device also provides a duplicate of the paf flag on the paf [7:0] flag bus, this will be discussed in detail in a later section of the data sheet. see figures 23 and 24 for almost full flag timing and queue switching. almost empty flag as previously mentioned the multi-queue flow-control device provides a single programmable almost empty flag output, pae . the pae flag output provides a status of the almost empty condition for the active queue currently selected on the read port for read operations. internally the multi-queue flow- control device monitors and maintains a status of the almost empty condition of all queues within it, however only the queue that is selected for read operations has its empty status output to the pae flag. this dedicated flag is often referred to as the ?active queue almost empty flag?. the position of the pae flag boundary within a queue can be at any point within that queues depth. this location can be user programmed via the serial port or one of the default values (8 or 128) can be selected if the user has performed default programming. as mentioned, every queue within a multi-queue device has its own almost empty status, when a queue is selected on the read port, this status is output via the pae flag. the pae flag value for each queue is programmed during multi- queue device programming (along with the number of queues, queue depths and almost full values). the pae offset value, n, for a respective queue can be programmed to be anywhere between ?0? and ?d?, where ?d? is the total memory depth for that queue. the pae value of different queues within the same device can be different values. when queue switches are being made on the read port, the pae flag output will switch to the new queue and provide the user with the new queue status, on the third cycle after a new queue selection is made, on the same rclk cycle that data actually falls through to the output register from the new queue. that is, a new queue can be selected on the read port via the rdadd bus, raden enable and a rising edge of rclk. on the third rising edge of rclk following a queue selection, the data word from the new queue will be available at the output register and the pae flag output will show the empty status of the newly selected queue. the pae is flag output is triple register buffered, so when a read operation occurs at the almost empty boundary causing the selected queue status to go almost empty the pae will go low 3 rclk cycles after the read. the same is true when a write occurs, there will be a 3 rclk cycle delay after the write operation. so the pae flag delays are: from a read operation to pae flag low is 2 rclk + t rae the delay from a write operation to pae flag high is t skew2 + rclk + t rae note, if t skew is violated there will be one added rclk cycle delay. the pae flag is synchronous to the rclk and all transitions of the pae flag occur based on a rising edge of rclk. internally the multi-queue device monitors and keeps a record of the almost empty status for all queues. it is possible that the status of a pae flag maybe changing internally even though that flag is not the active queue flag (selected on the read port). a queue selected on the write port may experience a change of its internal almost empty flag status based on write operations. the multi-queue flow-control device also provides a duplicate of the pae flag on the pae [7:0] flag bus, this will be discussed in detail in a later section of the data sheet. see figures 25 and 26 for almost empty flag timing and queue switching. power down (pd) this device has a power down feature intended for reducing power consumption for hstl/ehstl configured inputs when the device is idle for a long period of time. by entering the power down state certain inputs can be disabled, thereby significantly reducing the power consumption of the part. all wen and ren signals must be disabled for a minimum of four wclk and rclk cycles before activating the power down signal. the power down signal is asynchronous and needs to be held low throughout the desired power down time. during power down, the following c onditions for the inputs/outputs signals are: ? all data in queue(s) memory are retained. ? all data inputs become inactive. ? all write and read pointers maintain their last value before power down. ? all enables, chip selects, and clock input pins become inactive. ? all data outputs become inactive and enter high-impedance state. ? all flag outputs will maintain their current states before power down. ? all programmable flag offsets maintain their values. ? all echo clocks and enables will become inactive and enter high- impedance state. ? the serial programming and jtag port will become inactive and enter high-impedance state. ? all setup and configuration cmos static inputs are not affected, as these pins are tied to a known value and do not toggle during operation. all internal counters, registers, and flags will remain unchanged and maintain their current state prior to power down. clock inputs can be continuous and free- running during power down, but will have no affect on the part. however, it is recommended that the clock inputs be low when the power down is active. to exit power down state and resume normal operations, disable the power down signal by bringing it high. there must be a minimum of 1 s waiting period before read and write operations can resume. the device will continue from where it had stopped and no form of reset is required after exiting power down state. the power down feature does not provide any power savings when the inputs are configured for lvttl operation. however, it will reduce the current for i/os that are not tied directly to v cc or gnd. see figure 34, power down operation, for the associated timing diagram.
27 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges table 4 flag operation boundaries & timing output valid, ov flag boundary i/o set-up ov boundary condition in36 to out36 (almost empty mode) ov goes low after 1 st write (both ports selected for same queue (see note 1 below for timing) when the 1 st word is written in) in36 to out36 (packet mode) ov goes low after 1 st write (both ports selected for same queue (see note 2 below for timing) when the 1 st word is written in) in36 to out18 ov goes low after 1 st write (both ports selected for same queue (see note 1 below for timing) when the 1 st word is written in) in36 to out9 ov goes low after 1 st write (both ports selected for same queue (see note 1 below for timing) when the 1 st word is written in) in18 to out36 ov goes low after 1 st write (both ports selected for same queue (see note 1 below for timing) when the 1 st word is written in) in9 to out36 ov goes low after 1 st write (both ports selected for same queue (see note 1 below for timing) when the 1 st word is written in) note: 1. ov timing assertion: write to ov low: t skew1 + rclk + t rov if t skew1 is violated there may be 1 added clock: t skew1 + 2 rclk + t rov de-assertion: read operation to ov high: t rov 2. ov timing when in packet mode (36 in to 36 out only) assertion: write to ov low: t skew4 + rclk + t rov if t skew4 is violated there may be 1 added clock: t skew4 + 2 rclk + t rov de-assertion: read operation to ov high: t rov note: d = queue depth ff timing assertion: write operation to ff low: t wff de-assertion: read to ff high: t skew1 + t wff if t skew1 is violated there may be 1 added clock: t skew1 +wclk +t wff full flag, ff boundary i/o set-up ff boundary condition in36 to out36 ff goes low after d+1 writes (both ports selected for same queue (see note below for timing) when the 1 st word is written in) in36 to out36 ff goes low after d writes (write port only selected for queue (see note below for timing) when the 1 st word is written in) in36 to out18 ff goes low after d writes (both ports selected for same queue (see note below for timing) when the 1 st word is written in) in36 to out18 ff goes low after d writes (write port only selected for queue (see note below for timing) when the 1 st word is written in) in36 to out9 ff goes low after d writes (both ports selected for same queue (see note below for timing) when the 1 st word is written in) in36 to out9 ff goes low after d writes (write port only selected for queue (see note below for timing) when the 1 st word is written in) in18 to out36 ff goes low after ([d+1] x 2) writes (both ports selected for same queue (see note below for timing) when the 1 st word is written in) in18 to out36 ff goes low after (d x 2) writes (write port only selected for queue (see note below for timing) when the 1 st word is written in) in9 to out36 ff goes low after ([d+1] x 4) writes (both ports selected for same queue (see note below for timing) when the 1 st word is written in) in9 to out36 ff goes low after (d x 4) writes (write port only selected for queue (see note below for timing) when the 1 st word is written in) programmable almost full flag, paf & paf n bus boundary i/o set-up paf & paf n boundary in36 to out36 paf / paf n goes low after (both ports selected for same queue when the 1 st d+1-m writes word is written in until the boundary is reached) (see note below for timing) in36 to out36 paf / paf n goes low after (write port only selected for same queue when the d-m writes 1 st word is written in until the boundary is reached) (see note below for timing) in36 to out18 paf / paf n goes low after d-m writes (see below for timing) in36 to out9 paf / paf n goes low after d-m writes (see below for timing) in18 to out36 paf / paf n goes low after ([d+1-m] x 2) writes (see note below for timing) in9 to out36 paf / paf n goes low after ([d+1-m] x 4) writes (see note below for timing) note: d = queue depth m = almost full offset value. default values: if df is low at master reset then m = 8 if df is high at master reset then m= 128 paf timing assertion: write operation to paf low: 2 wclk + t waf de-assertion: read to paf high: t skew2 + wclk + t waf if t skew2 is violated there may be 1 added clock: t skew2 + 2 wclk + t waf paf n timing assertion: write operation to paf n low: 2 wclk* + t paf de-assertion: read to paf n high: t skew3 + wclk* + t paf if t skew3 is violated there may be 1 added clock: t skew3 + 2 wclk* + t paf * if a queue switch is occurring on the write port at the point of flag assertion or de-assertion there may be one additional wclk clock cycle delay.
28 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits table 4 flag operation boundaries & timing (continued) note: n = almost empty offset value. default values: if df is low at master reset then n = 8 if df is high at master reset then n = 128 pae n timing assertion: read operation to pae n low: 2 rclk* + t pae de-assertion: write to pae n high: t skew3 + rclk* + t pae if t skew3 is violated there may be 1 added clock: t skew3 + 2 rclk* + t pae * if a queue switch is occurring on the read port at the point of flag assertion or de-assertion there may be one additional rclk clock cycle delay. programmable almost empty flag bus, pae n boundary i/o set-up pae n boundary condition in36 to out36 pae n goes high after (both ports selected for same queue when the 1 st n+2 writes word is written in until the boundary is reached) (see note below for timing) in36 to out36 pae n goes high after (write port only selected for same queue when the n+1 writes 1 st word is written in until the boundary is reached) (see note below for timing) in36 to out18 pae n goes high after n+1 writes (see below for timing) in36 to out9 pae n goes high after n+1 writes (see below for timing) in18 to out36 pae n goes high after (both ports selected for same queue when the 1 st ([n+2] x 2) writes word is written in until the boundary is reached) (see note below for timing) in18 to out36 pae n goes high after (write port only selected for same queue when the ([n+1] x 2) writes 1 st word is written in until the boundary is reached) (see note below for timing) in9 to out36 pae n goes high after (both ports selected for same queue when the 1 st ([n+2] x 4) writes word is written in until the boundary is reached) (see note below for timing) in9 to out36 pae n goes high after (write port only selected for same queue when the ([n+1] x 4) writes 1 st word is written in until the boundary is reached) (see note below for timing) note: n = almost empty offset value. default values: if df is low at master reset then n = 8 if df is high at master reset then n = 128 pae timing assertion: read operation to pae low: 2 rclk + t rae de-assertion: write to pae high: t skew2 + rclk + t rae if t skew2 is violated there may be 1 added clock: t skew2 + 2 rclk + t rae programmable almost empty flag, pae boundary i/o set-up pae assertion in36 to out36 pae goes high after n+2 (both ports selected for same queue when the 1 st writes word is written in until the boundary is reached) (see note below for timing) in36 to out18 pae goes high after n+1 (both ports selected for same queue when the 1 st writes word is written in until the boundary is reached) (see note below for timing) in36 to out9 pae goes high after n+1 (both ports selected for same queue when the 1 st writes word is written in until the boundary is reached) (see note below for timing) in18 to out36 pae goes high after (both ports selected for same queue when the 1 st ([n+2] x 2) writes word is written in until the boundary is reached) (see note below for timing) in9 to out36 pae goes high after (both ports selected for same queue when the 1 st ([n+2] x 4) writes word is written in until the boundary is reached) (see note below for timing) packet ready flag, pr boundary assertion: both the rising and falling edges of pr are synchronous to rclk. pr falling edge occurs upon writing the first teop marker, on input d35, (assuming a tsop marker, on input d34 has previously been written). i.e. a complete packet is available within a queue. timing: from wclk rising edge writing the teop word pr goes low after: t skew4 + 2 rclk + t pr if t skew4 is violated: pr goes low after t skew4 + 3 rclk + t pr (please refer to figure 19, data input (transmit) packet mode of operation, for timing diagram). de-assertion: pr rising edge occurs upon reading the last rsop marker, from output q34. i.e. there are no more complete packets available within the queue. timing: from rclk rising edge reading the rsop word the pr goes high after: 3 rclk + t pr (please refer to figure 20, data output (receive) packet mode of operation for timing diagram). packet ready flag bus, pr n boundary assertion: both the rising and falling edges of pr n are synchronous to rclk. pr n falling edge occurs upon writing the first teop marker, on input d35, (assuming a tsop marker, on input d34 has previously been written). i.e. a complete packet is available within a queue. timing: from wclk rising edge writing the teop word pr goes low after: t skew4 + 2 rclk* + t pae if t skew4 is violated pr n goes low after t skew4 + 3 rclk* + t pae *if a queue switch is occurring on the read port at the point of flag assertion there may be one additional rclk clock cycle delay. de-assertion: pr rising edge occurs upon reading the last rsop marker, from output q34. i.e. there are no more complete packets available within the queue. timing: from rclk rising edge reading the rsop word the pr goes high after: 3 rclk* + t pae *if a queue switch is occurring on the read port at the point of flag assertion or de-assertion there may be one additional rclk clock cycle delay.
29 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges paf n - direct bus if fm is low at master reset then the paf n bus operates in direct (addressed) mode. in direct mode the user can address the quadrant of queues they require to be placed on to the paf n bus. for example, consider the operation of the paf n bus when 26 queues have been setup. to output status of the first quadrant, queue[0:7] the wradd bus is used in conjunction with the fstr ( paf flag strobe) input and wclk. the address present on the 2 least significant bits of the wradd bus with fstr high will be selected as the quadrant address on a rising edge of wclk. so to address quadrant 1, queue[0:7] the wradd bus should be loaded with ?xxxxxx00?, the paf n bus will change status to show the new quadrant selected 1 wclk cycle after quadrant selection. paf n[0:7] gets status of queues, queue[0:7] respectively. to address the second quadrant, queue[8:15], the wradd address is ?xxxxxx01?. paf n[0:7] gets status of queues, queue[8:15] respectively. to address the third quadrant, queue[16:23], the wradd address is ?xxxxxx10?. paf [0:7] gets status of queues, queue[16:23] respectively. to address the fourth quadrant, queue[24:31], the wradd address is ?xxxxxx11?. paf [0:1] gets status of queues, queue[24:25] respectively. remember, only 26 queues were setup, so when quadrant 4 is selected the unused outputs paf [2:7] will be don't care states. note, that if a read or write operation is occurring to a specific queue, say queue ?x? on the same cycle as a quadrant switch which will include the queue ?x?, then there may be an extra wclk cycle delay before that queues status is correctly shown on the respective output of the paf n bus. however, the active paf flag will show correct status at all times. quadrants can be selected on consecutive clock cycles, that is the quadrant on the paf n bus can change every wclk cycle. also, data present on the input bus, din, can be written into a queue on the same wclk rising edge that a quadrant is being selected, the only restriction being that a write queue selection and paf n quadrant selection cannot be made on the same cycle. if 8 or less queues are setup then queues, queue[0:7] have their paf status output on paf [0:7] constantly. when the multi-queue devices are connected in expansion of more than one device the paf n busses of all devices are connected together, when switching between quadrants of different devices the user must utilize the 3 most significant bits of the wradd address bus (as well as the 2 lsb?s). these 3 msb?s correspond to the device id inputs, which are the static inputs, id0, id1 & id2. please refer to figure 29 paf n - direct mode quadrant selection for timing information. also refer to table 1, write address bus, wradd . paf n ? polled bus if fm is high at master reset then the paf n bus operates in polled (looped) mode. in polled mode the paf n bus automatically cycles through the 4 quadrants within the device regardless of how many queues have been setup in the part. every rising edge of the wclk causes the next quadrant to be loaded on the paf n bus. the device configured as the master (mast input tied high), will take control of the paf n after mrs goes low. for the whole wclk cycle that the first quadrant is on paf n the fsync ( paf n bus sync) output will be high, for all other quadrants, this fsync output will be low. this fsync output provides the user with a mark with which they can synchronize to the paf n bus, fsync is always high for the wclk cycle that the first quadrant of a device is present on the paf n bus. when devices are connected in expansion mode, only one device will be set as the master, mast input tied high, all other devices will have mast tied low. the master device is the first device to take control of the paf n bus and will place its first quadrant on the bus on the rising edge of wclk after the mrs input goes high. for the next 3 wclk cycles the master device will maintain control of the paf n bus and cycle its quadrants through it, all other devices hold their paf n outputs in high-impedance. when the master device has cycled all of its quadrants it passes a token to the next device in the chain and that device assumes control of the paf n bus and then cycles its quadrants and so on, the paf n bus control token being passed on from device to device. this token passing is done via the fxo outputs and fxi inputs of the devices (? paf expansion out? and ? paf expansion in?). the fxo output of the master device connects to the fxi of the second device in the chain and the fxo of the second connects to the fxi of the third and so on. the final device in a chain has its fxo connected to the fxi of the first device, so that once the paf n bus has cycled through all quadrants of all devices, control of the paf n will pass to the master device again and so on. the fsync of each respective device will operate independently and simply indicate when that respective device has taken control of the bus and is placing its first quadrant on to the paf n bus. when operating in single device mode the fxi input must be connected to the fxo output of the same device. in single device mode a token is still required to be passed into the device for accessing the paf n bus. please refer to figure 32, paf n bus ? polled mode for timing information. pae n/ pr n flag bus operation the IDT72T51546/72t51556 multi-queue flow-control device can be configured for up to 32 queues, each queue having its own almost empty/ packet ready status. an active queue has its flag status output to the discrete flags, ov , pae and pr , on the read port. queues that are not selected for a read operation can have their pae / pr status monitored via the pae n/ pr n bus. the pae n/ pr n flag bus is 8 bits wide, so that 8 queues at a time can have their status output to the bus. if 9 or more queues are setup within a device then there are 2 methods by which the device can share the bus between queues, "direct" mode and "polled" mode depending on the state of the fm (flag mode) input during a master reset. if 8 or less queues are setup within a device then each will have its own dedicated output from the bus. if 8 or less queues are setup in single device mode, it is recommended to configure the paf n bus to polled mode as it does not require using the write address (wradd). pae n/ pr n - direct bus if fm is low at master reset then the pae n/ pr n bus operates in direct (addressed) mode. in direct mode the user can address the quadrant of queues they require to be placed on to the pae n/ pr n bus. for example, consider the operation of the pae n/ pr n bus when 26 queues have been setup. to output status of the first quadrant, queue[0:7] the rdadd bus is used in conjunction with the estr ( pae / pr flag strobe) input and rclk. the address present on the 2 least significant bits of the rdadd bus with estr high will be selected as the quadrant address on a rising edge of rclk. so to address quadrant 1, queue[0:7] the rdadd bus should be loaded with ?xxxxxx00?, the pae n/ pr n bus will change status to show the new quadrant selected 1 rclk cycle after quadrant selection. pae n[0:7] gets status of queues, queue[0:7] respectively. to address the second quadrant, queue[8:15], the rdadd address is ?xxxxxx01?. pae n[0:7] gets status of queues, queue[8:15] respectively. to address the third quadrant, queue[16:23], the rdadd address is ?xxxxxx10?. pae [0:7] gets status of queues, queue[16:23] respectively. to address the fourth quadrant, queue[24:31], the rdadd address is ?xxxxxx11?. pae [0:1] gets status of queues, queue[24:25] respectively. remember, only 26 queues were setup, so when quadrant 4 is selected the unused outputs pae [2:7] will be don't care states. note, that if a read or write operation is occurring to a specific queue, say queue ?x? on the same cycle as a quadrant switch which will include the queue ?x?, then there may be an extra rclk cycle delay before that queues status is correctly shown on the respective output of the pae n/ pr n bus.
30 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits quadrants can be selected on consecutive clock cycles, that is the quadrant on the pae n/ pr n bus can change every rclk cycle. also, data can be read out of a queue on the same rclk rising edge that a quadrant is being selected, the only restriction being that a read queue selection and pae n/ pr n quadrant selection cannot be made on the same rclk cycle. if 8 or less queues are setup then queues, queue[0:7] have their pae / pr status output on pae [0:7] constantly. when the multi-queue devices are connected in expansion of more than one device the pae n/ pr n busses of all devices are connected together, when switching between quadrants of different devices the user must utilize the 3 most significant bits of the rdadd address bus (as well as the 2 lsb?s). these 3 msb?s correspond to the device id inputs, which are the static inputs, id0, id1 & id2. please refer to figure 28, pae n/ pr n - direct mode quadrant selection for timing information. also refer to table 2, read address bus, rdadd . pae n ? polled bus if fm is high at master reset then the pae n/ pr n bus operates in polled (looped) mode. in polled mode the pae n/ pr n bus automatically cycles through the 4 quadrants within the device regardless of how many queues have been setup in the part. every rising edge of the rclk causes the next quadrant to be loaded on the pae n/ pr n bus. the device configured as the master (mast input tied high), will take control of the pae n/ pr n after mrs goes low. for the whole rclk cycle that the first quadrant is on pae n/ pr n the esync ( pae n/ pr n bus sync) output will be high, for all other quadrants, this esync output will be low. this esync output provides the user with a mark with which they can synchronize to the pae n/ pr n bus, esync is always high for the rclk cycle that the first quadrant of a device is present on the pae n/ pr n bus. when devices are connected in expansion mode, only one device will be set as the master, mast input tied high, all other devices will have mast tied low. the master device is the first device to take control of the pae n/ pr n bus and will place its first quadrant on the bus on the rising edge of rclk after the mrs input goes low. for the next 3 rclk cycles the master device will maintain control of the pae n/ pr n bus and cycle its quadrants through it, all other devices hold their pae n/ pr n outputs in high-impedance. when the master device has cycled all of its quadrants it passes a token to the next device in the chain and that device assumes control of the pae n/ pr n bus and then cycles its quadrants and so on, the pae n/ pr n bus control token being passed on from device to device. this token passing is done via the exo outputs and exi inputs of the devices (? pae expansion out? and ? pae expansion in?). the exo output of the master device connects to the exi of the second device in the chain and the exo of the second connects to the exi of the third and so on. the final device in a chain has its exo connected to the exi of the first device, so that once the pae n/ pr n bus has cycled through all quadrants of all devices, control of the pae n/ pr n will pass to the master device again and so on. the esync of each respective device will operate independently and simply indicate when that respective device has taken control of the bus and is placing its first quadrant on to the pae n/ pr n bus. when operating in single device mode the exi input must be connected to the exo output of the same device. in single device mode a token is still required to be passed into the device for accessing the pae n bus. please refer to figure 33, pae n/ pr n bus ? polled mode for timing information.
31 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges echo read clock (erclk) the echo read clock output is provided in both hstl and lvttl mode, selectable via iosel. the erclk is a free-running clock output, it will always follow the rclk input regardless of ren and raden. the erclk output follows the rclk input with an associated delay. this delay provides the user with a more effective read clock source when reading data from the qn outputs. this is especially helpful at high speeds when variables within the device may cause changes in the data access times. these variations in access time maybe caused by ambient temperature, supply voltage, device characteristics. the erclk output also compensates for any trace length delays between the qn data outputs and receiving devices inputs. any variations effecting the data access time will also have a corresponding effect on the erclk output produced by the queue device, therefore the erclk output level transitions should always be at the same position in time relative to the data outputs. note, that erclk is guaranteed by design to be slower than the slowest qn, data output. refer to figure 3, echo read clock and data output relationship and figure 27, echo rclk & echo ren operation for timing information. echo read enable ( eren ) the echo read enable output is provided in both hstl and lvttl mode, selectable via iosel. the eren output is provided to be used in conjunction with the erclk output and provides the reading device with a more effective scheme for reading data from the qn output port at high speeds. the eren output is controlled by internal logic that behaves as follows: the eren output is active low for the rclk cycle that a new word is read out of the queue. that is, a rising edge of rclk will cause eren to go active (low) if ren is active and the queue is not empty. figure 3. echo read clock and data output relationship notes: 1. ren is low. oe is low. 2. t erclk > t a , guaranteed by design. 3. qslowest is the data output with the slowest access time, t a . 4. time, t d is greater than zero, guaranteed by design. 5998 drw08 erclk t a t d q slowest (3) rclk t erclk t erclk
32 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits d b c a (c) x36 input to x9 output 1st: read from queue 2nd: read from queue 3rd: read from queue 4th: read from queue 5998 drw09 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 a c b b d a cd (a) x36 input to x36 output (b) x36 input to x18 output read from queue l bm iw ow ll 1st: read from queue 2nd: read from queue byte order on output port: q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 a c b d 1st: write to queue 2nd: write to queue 3rd: write to queue 4th: write to queue byte order on input port: dcb a (e) x9 input to x36 output read from queue byte order on output port: d35-d27 d26-d18 d17-d9 d8-d0 d35-d27 d26-d18 d17-d9 d8-d0 d35-d27 d26-d18 d17-d9 d8-d0 d35-d27 d26-d18 d17-d9 d8-d0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 c a d d b c a b d35-d27 d26-d18 d17-d9 d8-d0 (d) x18 input to x36 output read from queue byte order on input port: d35-d27 d26-d18 d17-d9 d8-d0 1st: write to queue 2nd: write to queue byte order on output port: d35-d27 d26-d18 d17-d9 d8-d0 abc d write to queue byte order on input port: h bm iw ow ll h bm iw ow lh h bm iw ow hl h bm iw ow hh figure 4. bus-matching byte arrangement
33 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges ov t rsf paf t rsf pae t rsf t rsf t rsf pr t rsf t rsf qn t rsf logic "1" if oe is low and device is master high-z if oe is high or device is slave logic "1" if master device high-z if slave device logic "1" if master device high-z if slave device high-z if slave device logic "0" if master device high-z if slave device logic "0" if master device logic "1" if master device high-z if slave device logic "1" if master device high-z if slave device logic "1" if master device high-z if slave device paf n pae n pr n t rs mrs wen ren t rss fstr, estr 5998 drw10 t rsr seni waden, raden t rss t rss t rss ow, iw, bm df fm high = looped low = strobed (direct) id0, id1, id2 t rss high = packet ready mode low = almost empty mast pkt dfm high = master device low = slave device high = default programming low = serial programming high = offset value is 128 low = offset value is 8 t rss t rss t rss t rss t rss t rss ff t rsf high-z if slave device logic "0" if master device figure 5. master reset notes: 1. oe can toggle during this period. 2. prs should be high during a mrs .
34 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits figure 7. serial port connection for serial programming dfm mrs seni seno mq1 si so sclk dfm mrs seni seno mq2 si so sclk dfm mrs seni seno mqn si so sclk serial enable serial input serial clock default mode dfm = 0 master reset serial loading complete 5998 drw12 figure 6. partial reset notes: 1. for a partial reset to be performed on a queue, that queue must be selected on both the write and read ports. 2. the queue must be selected a minimum of 3 clock cycles before the partial reset takes place, on both the write and read ports . 3. the partial reset must be low for a minimum of 1 wclk and 1 rclk cycle. 4. writing or reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the partial reset ha s gone high, on both the write and read ports. 5. the paf flag output for qx on the paf n flag bus may update one cycle later than the active paf flag. 6. the pae flag output for qx on the pae n flag bus may update one cycle later than the active pae flag. wclk rclk rdadd t ah t as t qh t qs qx raden r-2 r-1 r t prsh t prss t prsh t prss prs r+3 r+1 t ens ren r+4 t ens t rov ov t rae pae 5998 drw11 t ens w+1 w+2 w+3 t wff t waf t paf wen waden t ah t as wradd qx w-3 w-2 w-1 t qh t qs t ens ff paf active bus paf -qx (5) active bus pae -qx (6) t pae w r+2
35 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges figure 8. serial programming rclk wen seno (mq1) ff waden/ fstr raden/ estr ov wclk 5998 drw13 t wff t ens t rov t pcwq t qs t qh t qs t qh t pcrq high - z high - z (slave device) (slave device) so (mq1) mrs sclk seni (mq1) si (mq1) t rsr t seno 1st 2nd nth 1st 2nd nth 1st 2nd nth t sens seno (mq2) seno (mq8) b 12 b 11 t sds b 1n t sdh b 21 b 22 b 2n b 81 b 82 b 8n b 21 b 22 b 2n b 81 b 82 b 8n t seno t seno t sclk t sckl t sckh programming complete 1st device in chain 2nd device in chain final device in chain t sdo t sdop t senop t senop notes: 1. seni can be toggled during serial loading. once serial programming of a device is complete, the seni and si inputs become transparent. seni seno and si so. 2. dfm is low during master reset to provide serial programming mode, df is don't care. 3. when seno of the final device is low no further serial loads will be accepted. 4. n = 19+(qx72); where q is the number of queues required for the IDT72T51546/72t51556. 5. this diagram illustrates 8 devices in expansion. 6. programming of all devices must be complete ( seno of the final device is low), before any write or read port operations can take place, this includes queue selections.
36 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits figure 9. default programming dfm mrs seni seno mq1 wclk serial enable (can be tied low) wclk default mode dfm = 1 master reset serial loading complete dfm mrs seni seno mq2 wclk dfm mrs seni seno mqn wclk rclk wen ff waden/ fstr raden/ estr ov 5998 drw14 t wff t ens t rov t pcwq t qs t qh t qs t qh t pcrq high - z high - z (slave device) (slave device) seno (mq1) t seno seno (mq2) seno (mq8) t seno wclk mrs 1st device in chain 1st 2nd nth 3rd 2nd device in chain 1st 2nd nth final device in chain 1st 2nd nth programming complete t seno serial port connection for default programming si so xsi so xsi so x notes: 1. this diagram illustrates multiple devices connected in expansion. the seno of the final device in a chain is the "programming complete" signal. 2. seni of the first device in the chain can be held low 3. the seno of a device should connect to the seni of the next device in the chain. the final device seno is used to indicate programming complete. 4. when default programming is complete the seno of the final device will go low. 5. sclk is not used and can be tied low. 6. programming of all devices must be complete ( seno of the final device is low), before any write or read port operations can take place, this includes queue selections.
37 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges figure 10. write queue select, write operation and full flag operation wclk 5998 drw15 t skew1 t qs t qh t ens q y t a previous q, word, w previous q, w +1 pft t a t a qy, w 0 qy, w 1 t as t ah *aa* *bb* *cc* *dd* *ee* *ff* t ens t ah t as q y t qh t qs t dh t ds q x w d t dh q y w d-2 t dh t ds q y w d t ds t dh t ds t wff t wff t wff no writes queue full *c* *d* *e* *f* *g* *h* t enh *i* *j* *k* waden t qh t qs t ah t as wradd q x ff wen din previous q status *a* rclk ren rdadd raden qout *b* t a *gg* t wff t wff *l* no writes queue full q y w d-1 qy, w 2 123 note : oe is active low. cycle: *a* queue, qx is selected on the write port. the ff flag is providing status of a previously selected queue, within the same device. *aa* queue, qy is selected for read operations. *b* the ff flag provides status of previous queue for 3 wclk cycles. *bb* current word is kept on the output bus since ren is high. *c* the ff flag output updates to show the status of qx, it is not full. *cc* word w+1 is read from the previous queue regardless of ren due to fwft. *d* word, wd is written into qx. this causes qx to go full. *dd* the next available word w0 of qy is read out regardless of ren , 3 rclk cycles after queue selection. this is fwft operation. *e* queue, qy is selected within the same device as qx. a write to qx cannot occur on this cycle because it is full, ff is low. *ee* no reads occur, ren is high. *f* again, a write to qx cannot occur on this cycle because it is full, ff is low. *ff* word, w1 is read from qy, this causes qy to go ?not full?, ff flag goes high after time, t skew1 + t wff . note, if t skew1 is violated the time ff high will be: t skew1 + wclk + t wff . *g* the ff flag updates after time t wff to show that queue, qy is not full. *gg* word, w2 is read from qy. *h* word, wd-2 is written into qy. *i* word, wd-1 is written into qy. *j* word, wd is written into qy, this causes qy to go full, ff goes low. *k* a write to qy cannot occur on this cycle because it is full, ff is low. *l* qy goes ?not full? based on reading word w1 from qy on cycle *ff*.
38 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits 5998 drw16 w1 w2 w3 wclk t enh wen dn t dh t ds t ds t dh t ds t dh rclk t skew1 12 t ens ren t a w1 qy fwft t a t a w2 qy fwft w3 qy last word read out of queue qout t rov ov t rov t ens figure 11. write operations & first word fall through notes: 1. qy has previously been selected on both the write and read ports. 2. oe is low. 3. the first word latency = t skew1 + rclk + t a . if t skew1 is violated an additional rclk cycle must be added.
39 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges wclk t fflz 5998 drw17 1 2 t skew1 t ah t as d 1 q 5 t q h t qs t a previous q w x-1 d 1 -q 5 word w 0 pft *aa* *bb* *cc* t ens t ah t as t ah t as t qh t qs d 2 q 9 t qh t qs t dh t ds w d d 1 q27 t dh t ds t wff w d d 1 q5 t wff t wff t enh t ens t enh d 1 q 5 t ffhz t wff high-z t ffhz high-z t fflz addr=001 00101 *c* *d* *e* *f* *g* *h* *i* *j* no write *k* waden t qh t qs t ah t as wradd d 1 q 27 ff (device 1) wen din high-z rclk addr=001 11011 ff (device 2) rdadd raden *a* qout *b* *dd* 3 t a previous q w x pft figure 12. full flag timing in expansion mode note: 1. ren = high. cycle: *a* queue, q27 of device 1 is selected on the write port. the ff flag of device 1 is in high-impedance, the write port of device 2 was previously selected. wen is high so no write occurs. *aa* queue, q5 of device 1 is selected on the read port. *b* the ff flag stays in high-impedance for 2 wclk cycles. *bb* word, wx-1 is held on the outputs for 2 rclk cycles after a read queue switch. *c* the ff flag of device 2 goes to high-impedance and the ff flag of device 1 goes to low-impedance, logic high indicating that d1 q27 is not full. wen is high so no write occurs. *cc* word, wx is read from the previously selected queue, (due to fwft). *d* word, wd is written into q27 of d1. this write operation causes q27 to go full, ff goes low. *dd* the first word from q5 of d1 selected on cycle *aa* is read out, this occurred regardless of ren due to fwft. this read caused q5 to go not full, therefore the ff flag will go high after: t skew1 + t wff . note if t skew1 is violated the time to ff flag high is t skew1 + wlck + t wff . *e* queue, q5 of device 1 is selected on the write port. no write occurs on this cycle. *f* the ff flag stays in high-impedance for 2 wclk cycles. *g* the ff flag updates to show the status of d1 q5, it is not full, ff goes high. *h* word, wd is written into q5 of d1. this causes the queue to go full, ff goes low. *i* no write occurs regardless of wen , the ff flag is low preventing writes. the ff flag goes high due to the read from q5 of d1 on cycle *cc*. (this read is not an enabled read, it is due to the fwft operation ). *j* queue, q9 of device 2 is selected on the write port. *k* the ff flag of device 1 goes to high-impedance, this device was deselected on the write port on cycle *i*. the ff flag of device 2 goes to low-impedance and provides status of q9 of d2.
40 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits figure 13. read queue select, read operation rclk 5998 drw18 t ah t as q f rdadd t qh t qs raden ren t ens t enh t ens t ah t as q g t qh t qs q out q p w n-3 t a q p w n-2 t a previous q, q p w n-1 t a t a q p w n t a q p w n+1 pft t a q f w 0 q f w 1 t rov ov previous q 1 2 *a* *b* *c* *d* *e* *f* *g* *h* pft *i* t a q f w 2 *j* 3 cycle: *a* word wn- 3 is read from a previously selected queue qp on the read port. *b* wn- 2 is read. *c* reads are disabled, wn- 1 remains on the output bus. *d* a new queue, q f is selected for read operations. *e* word wn- 1 in qp is read out. *f* the next word available in current queue q p , wn+ 1 is read regardless of ren due to fwft. *g* the next word available in the new queue, q f -w 0 falls through to the output bus, again this is regardless of ren . a new queue, q g is selected for read operations. (this queue is an empty queue). *h* word, w 1 is read from q f . *i* word, w 2 is read from q f . *j* word w 2 from q f remains on the output bus because q g is empty. the output valid flag, ov goes high to indicate that the current word is not valid, i.e. q g is empty. w 2 is the last word in q g .
41 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges figure 14. output valid flag timing (in expansion mode) 5998 drw19 t ah t as t qh t qs t rov d 1 q 15 t rov t ovhz t skew1 t ah t as d 1 q 15 t q h t qs t dh t ds d 1 q 15 w 0 t a d 1 q 30 w d last word t olz t a d 1 q 15 pft w e-1 t a d 1 q 15 w e last word t a w 0 q 15 d 1 t ovlz t rov t rov t ens t enh *d* *e* *f* *g* *h* *i* *j* rclk raden t qh t qs t ah t as rdadd d 1 q 30 ov (device 1) t ens ren qout (device 1) high-z wclk ov (device 2) wradd waden din wen *a* *b* *c* cycle: *a* queue 30 of device 1 is selected for read operations. the ov is currently being driven by device 2, a queue within device 2 is selected for reads. device 2 also has control of qout bus, its qout outputs are in low-impedance. this diagram only shows the qout outputs of device 1. (reads are disabled). *b* reads are now enabled. a word from the previously selected queue of device 2 will be read out. *c* after a queue switch, there is a 3 rclk latency for output data. *d* the qout of device 1 goes to low-impedance and word wd is read from q30 of d1. this happens to be the last word of q30. device 2 places its qout outputs into high-impedance, device 1 has control of the qout bus. the ov flag of device 2 goes to high-impedance and device 1 takes control of ov . the ov flag of device 1 goes low to show that wd of q30 is valid. *e* queue 15 of device 1 is selected for read operations. the last word of q30 was read on the previous cycle, therefore ov goes high to indicate that the data on the qout is not valid (q30 was read to empty). word, wd remains on the output bus. *f* the last word of q30 remains on the qout bus, ov is high, indicating that this word has been previously read. *g* the next word (we-1), available from the newly selected queue, q15 of device 1 is now read out. this will occur regardless of ren , 2 rclk cycles after queue selection due to the fwft operation. the ov flag updates 3 rclk cycles after a queue selection. *h* the last word, we is read from q15, this queue is now empty. *i* the ov flag goes high to indicate that q15 was read to empty on the previous cycle. *j* due to a write operation the ov flag goes low and data word w0 is read from q15. the latency is: t skew1 + 1*rclk + t rov .
42 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits figure 15. read queue selection with reads disabled rclk 5998 drw20 t ens t ah t as q p t q h t qs t a q n w x+1 t a q p w d+3 t a t enh q n w x t ah t as q n rdadd t qh t qs raden ren q out q p w d t a q p w d+1 t a q p w d+2 ov t ens t enh *a* *b* *c* *d* *e* *f* *g* *h* *i* *j* *k* *l* q n w x+2 t a t ens t enh 123 q p w d+3 t a 123 cycle: *a* word wd+1 is read from the previously selected queue, qp. *b* reads are disabled, word wd+1 remains on the output bus. *c* a new queue, qn is selected for read port operations. *d* word, w d +2 of qp is read out. *e* word w d +3 of qp is read out regardless of ren due to fwft operation. *f* the next available word wx of qn is read out regardless of ren , 3 rclk cycles after queue selection. this is fwft operation. *g* the queue, qp is again selected. *h* current word is kept on the output bus since ren is high. *i* word wx+2 is read from qn. this is read out regardless of ren due to fwft operation. *j* word w d +3 is read from qp. *k* word w d +4 is read from qp. *l* reads are disabled on this cycle, therefore no further reads occur.
43 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges figure 16. read queue select, read operation and oe timing rclk 5998 drw21 t a q a w 0 pft t a t a t ens t ah t as q b t qh t qs t a t a q a w 1 t rov *d* *f* *g* *e* *i* *j* *h* t enh t ens q a w 2 q a w 3 q a w 4 t ohz raden t qh t qs t ah t as rdadd q a ov qout t olz ren oe t oe previous data in o/p register *b* *a* *c* t rov no read q b is empty *k* 12 3 12 3 t a notes: 1. the output valid flag, ov is high therefore the previously selected queue has been read to empty. the output enable input is asynchronous, therefore the qout output bus will go to low-impedance after time t olz . the data currently on the output register will be available on the output after time t oe . this data is the previous data on the output register, this is the last word read out of the previous queue. 2. in expansion mode the oe inputs of all devices should be connected together. this allows the output busses of all devices to be high-impedance controll ed. cycle: *a* queue a is selected for reads. no data will fall through on this cycle, the previous queue was read to empty. *b* no data will fall through on this cycle, the previous queue was read to empty. *c* previous data kept on output bus since there is no read operation. *d* word, w0 from q a is read out regardless of ren due to fwft operation. the ov flag goes low indicating that word w0 is valid. *e* reads are disabled therefore word, w0 of q a remains on the output bus. *f* reads are again enabled so word w1 is read from q a . *g* word w2 is read from q a . *h* queue, q b is selected on the read port. this queue is actually empty. word, w3 is read from q a . *i* word, w4 is read from q a . *j* output enable is taken high, this is asynchronous so the output bus goes to high-impedance after time, t ohz . *k* output valid flag, ov goes high to indicate that q b is empty. data on the output port is no longer valid.
44 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits figure 17. writing in packet mode during a queue change note: 1. do not write an sop or eop on "d" or "k". a filler word is needed. wclk q a wradd q b a q c waden din q a data q a data q a teop q a dummy q b tsop q b dummy q c tsop q b data q b data wen teop (d35) tsop (d35) q b t eop bc d (1) efgh i j t as t ah t as t ah t ds t dh t ds t dh 12 12 k (1) 5998 drw22
45 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges figure 18. reading in packet mode during a queue change note: 1. do not read an sop or eop on "e" or "l". a filler word is needed. rclk q a rdadd q b a q c raden qout q a data q a data q a reop q a ?dummy? q b rsop q b ?dummy? q b data q b data ren reop (q35) rsop (q34) q b r eop bcd e (1) fgh i j k l (1) q c rsop t as t ah t as t ah 12 12 t a t a t a t a t a t a t a t a 5998 drw23
46 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits t dh t dh t ens *a* *b* t enh p1wo p1wn p1wn -1 p1wn -2 p1wn -3 t dh t dh t dh t dh t dh t dh *c* t ds wclk tsop (d34) rclk teop (d35) pr t pr wen d0- d31 taeop/ tmod1 (d33) tmod2 (d32) 5998 drw24 ov t rov qn t a p1wo t skew5 last word read out t skew4 t ds t ds t ds t ds t ds t ds t ds figure 19. data input (transmit) packet mode of operation notes: 1. ren is high. 2. if t skew4 is violated pr may take one additional rclk cycle. 3. if t skew5 is violated the ov may take one additional rclk cycle. 4. pr will always go low on the same cycle or 1 cycle ahead of ov going low, (assuming the last word of the packet is the last word in the queue). 5. in packet mode, words cannot be read from a queue until a complete packet has been written into that queue, regardless of ren .
47 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges rsop (q34) reop (q35) t pr t a t ens ren q0-q31 p1wo p1wn p1w1 raeop/ rmod1 (q33) pr rmod2 (q32) rclk p1wn -1 p1wn -2 p1wn -3 *a* *b* *d* *e* 5998 drw35 ov t ro v t a t a t a t a t a t a t a p1w2 *c* figure 20. data output (receive) packet mode of operation note: 1. in packet mode, words cannot be read from a queue until a complete packet has been written into that queue, regardless of ren . 2. the pr flag will go high on cycle *c* regardless of ren . 3. the ov flag will go high (preventing further reads), when the last complete packet has been read out. if there is a partial packet (a n incomplete packet) in the queue the ov flag will remain high until further writes have completed the packet.
48 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits rclk raden qout ren t ah t as 00100000 rdadd t a null queue select *a* *b* *c* *e* *g* t a q4 w0 fwft t rov 5998 drw26 t qh t ens q1 wn-4 q1 wn-3 q1 wn-2 t a t a q1 wn t rov ov select new queue *d* 00000100 t ah t as t qh t qs t enh t qs t ah t as null-q *f* q1 wn-1 t a figure 21. read operation and null queue select notes: 1. the purpose of the null queue operation is so that the user can stop reading a block (packet) of data from a queue without fi lling the 2 stage output pipeline with the next words from that queue. 2. please see figure 22, null queue flow diagram . cycle: *a* null q of device 0 is selected, when word wn-3 from previously selected q1 is read. *c* ren is high and wn (last word of the packet) of q1 is pipelined onto the o/p register. note: *b* and *c* are a minimum 3 rclk cycles between queue selects. *d* the null q is seen as an empty queue on the read side, therefore wn of q1 remains in the o/p register and ov goes high. a new queue, q4 is selected. *g* 1st word, w0 of q4 falls through present on the o/p register after 3 rclk cycles after the queue select. queue 1 memory *a* *b* null queue *c* o/p reg. *d* *e* *f* null queue q1 wn queue 4 memory o/p reg. o/p reg. o/p reg. o/p reg. o/p reg. qn wn-2 q1 wn q1 wn-1 q1 wn q1 wn q1 wn q1 wn q1 wn q1 wn q4 w0 q1 wn queue 1 memory null queue 5998 drw27 *g* queue 4 memory o/p reg. q4 w1 q4 w0 figure 22. null queue flow diagram
49 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges wclk t aflz 5998 drw28 t ens t ah t as t qh t qs t dh t ds w d-m t waf t waf t enh d 1 q 9 t ffhz 1 2 d 1 q 5 *d* *f* *h* *e* waden t qh t qs t ah t as wradd d 1 q 5 paf (device 1) wen din high-z paf (device 2) *b* *a* *c* *g* figure 23. almost full flag timing and queue switch figure 24. almost full flag timing wclk wen paf rclk t waf ren 5998 drw29 d - (m+1) words in queue ( 2) d - m words in queue 1 2 1 d-(m+1) words in queue t waf t enh t ens t skew2 t enh t ens t clkl t clkl cycle: *a* queue 5 of device 1 is selected on the write port. a queue within device 2 had previously been selected. the paf output of device 1 is high-impedance. *b* no write occurs. *c* no write occurs. *d* word, wd-m is written into q5 causing the paf flag to go from low to high. the flag latency is 3 wclk cycles + t waf . *e* queue 9 in device 1 is now selected for write operations. this queue is not almost full, therefore the paf flag will update after a 3 wclk + t waf latency. *f* the paf flag goes low based on the write 2 cycles earlier. *g* no write occurs. *h* the paf flag goes high due to the queue switch to q9. note: 1. the waveform here shows the paf flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read from at the almost full boundary. flag latencies: assertion: 2*wclk + t waf de-assertion: t skew2 + wclk + t waf if t skew2 is violated there will be one extra wclk cycle.
50 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits figure 25. almost empty flag timing and queue switch figure 26. almost empty flag timing rclk raden t qh t qs t ah t as rdadd d 1 q 30 t ah t as d 1 q 15 pae (device 1) t aelz 5998 drw30 t olz t rae t rae t aehz t a d 1 q 30 w n t a d 1 q 30 w n+1 t a d 1 q 15 w 0 t a d 1 q 15 w 1 ren t qh t qs qout high-z pae (device 2) high high-z high-z *b* *c* *e* *f* *d* *a* *g* *h* wclk t enh t clkh t clkl wen pae rclk t ens n+1 words in queue t rae t skew2 t rae 12 ren 5998 drw31 t ens t enh n+2 words in queue n+1 words in queue cycle: *a* queue 30 of device 1 is selected on the read port. a queue within device 2 had previously been selected. the pae flag output and the data outputs of device 1 are high-impedance. *b* no read occurs. *c* no read occurs. *d* the pae flag output now switches to device 1. word, wn is read from q30 due to the fwft operation. this read operation from q30 is at the almost empty boundary, therefore pae will go low 2 rclk cycles later. *e* q15 of device 1 is selected. *f* the pae flag goes low due to the read from q30 2 rclk cycles earlier. word wn+1 is read out due to the fwft operation. *g* word, w0 is read from q15 due to the fwft operation. *h* the pae flag goes high to show that q15 is not almost empty. note: 1. the waveform here shows the pae flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read from at the almost empty boundary. flag latencies: assertion: 2*rclk + t rae de-assertion: t skew2 + rclk + t rae if t skew2 is violated there will be one extra rclk cycle.
51 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges figure 27. echo rclk and echo ren operation rclk 1 2 *a* *b* *c* *d* *e* *f* *g* *h* *i* 5998 drw32 t ah t as q f rdadd t q h t qs raden t ah t as q g t qh t qs q out q p w n-3 t a q p w n-2 t a previous q, q p w n-1 t a t a q p w n t a pft q f w 0 ov previous q pft ren t ens t enh t ens t erclk erclk 1 2 t clken t clken eren t clken t clken q p w n+1 t rov cycle: *a* eren follow ren provided that the current queue (qp) is not empty. *b* eren stays active since a new word (wn- 1 ) from qp is placed on the output bus. *c, d* eren goes high since no new word has been placed on the output bus on this cycle. *e* ren goes low, new word placed on output bus, so eren goes low. *f, g* eren stays active since a new word from qp has been placed on the output bus. *h* w 0 is the last word in q f thus ov goes high. *i* eren goes high since no new word has been placed on the output bus and q f is empty.
52 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits figure 28. pae n/ pr n - direct mode - quadrant selection rclk t sth t sts t qh t qs 001xxx10 5998 drw33 t qs t qh 001xxx11 device 1 quadrant 3 t qs t qh 001xxx00 device 1 quadrant 0 t sts t sth t pae device 1 quadrant 2 t pae device 1 quadrant 3 rdadd estr device 1 quadrant 2 pae n/ pr n t pae device 1 quadrant 0 figure 29. paf n - direct mode - quadrant selection wclk 5998 drw34 t qs t qh 001xxx11 device 1 quadrant 3 t qs t qh 001xxx10 device 1 quadrant 2 t sts t sth t paf t paf device 1 quadrant 1 device 1 quadrant 2 t paf device 1 quadrant 3 t sth t sts t qh t qs 001xxx01 wradd fstr device 1 quadrant 1 paf n notes: 1. quadrants can be selected on consecutive cycles. 2. on an rclk cycle that the estr is high, the raden input must be low. 3. there is a latency of 2 rclk for the pae n bus to switch. notes: 1. quadrants can be selected on consecutive cycles. 2. on a wclk cycle that the fstr is high, the waden input must be low. 3. there is a latency of 2 wclk for the paf n bus to switch.
53 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges wclk dn prev pae n rclk d5 quad 4 101 xxx11 t ah 1 t rae d5quad 4 d5quad 4 t paehz t paezl xxxx xxx1 xxxx xxx1 t skew3 xxxx xxx0 d5quad4 2 t sth t pae 5998 drw35 t rae *dd* *ee* *gg* *ff* xxxx xxx0 d5quad4 t enh t ens wy d5 q24 wy+1 d5 q24 wy+3 d5 q24 wy+2 d5 q24 wa+1 d5 q17 t a t a t a t a t dh d3q8 wn d5 q24 wn+1 d5q24 011 01000 d4 quad 3 100 xxx10 *d* *e* *f* *g* t qh t qs t ah t as t ah t as t enh t sth t sts 3 t ens t enh t rae d5 q24 status estr rdadd 100 11000 d5q24 t as t ah t as previous value loaded on to pae bus raden t qh t qs t sts device 5 pae *aa* *bb* d5 q17 status bus pae n previous value loaded on to pae bus ren device 5 -qn t a wa d5 q17 t ds wen waden fstr t ah 100 11000 t as wradd d5q24 *a* *b* t qh t qs t ens device 5 pae n 1 wp+1 wp writes to previous q t dh t ds t dh *c* 2 t qh t qs *h* wp+2 t ds wx d3 q8 *cc* 3 1 23 figure 30. pae n - direct mode, flag operation cycle: *a* queue 24 of device 5 is selected for write operations. word, wp is written into the previously selected queue. *aa* queue 24 of device 5 is selected for read operations. a quadrant from another device has control of the pae n bus. the discrete pae output of device 5 is currently in high-impedance and the pae active flag is controlled by the previously selected device. *b* word wp+1 is written into the previously selected queue. *bb* current word is kept on the output bus since ren is high. *c* word wp+2 is written into the previously selected queue. *cc* word wa+1 of d5 q17 is read due to fwft. *d* word, wn is written into the newly selected queue, q24 of d5. this write will cause the pae flag on the read port to go from low to high (not almost empty) after time, t skew3 + rclk + t rae (if t skew3 is violated one extra rclk cycle will be added). *dd* word, wy from the newly selected queue, q24 will be read out due to fwft operation. quadrant 4 of device 5 is selected on the pae n bus. q24 of device 5 will therefore have is pae status output on pae [0]. there is a single rclk cycle latency before the pae n bus changes to the new selection. *e* queue 8 of device 3 is selected for write operations. word wn+1 is written into q24 of d5. *ee* word, wy+1 is read from q24 of d5. *f* no writes occur. *ff* word, wy+2 is read from q24 of d5. the pae n bus changes control to d5, the pae n outputs of d5 go to low-impedance and quadrant 4 is placed onto the outputs. the device of the previously selected quadrant now places its pae n outputs into high-impedance to prevent bus contention. the discrete pae flag will go high to show that q24 of d5 is not almost empty. q24 of device 5 will have its pae status output on pae [0]. *g* quadrant 3 of device 4 is selected on the write port for the paf n bus. *gg* the pae n bus updates to show that q24 of d5 is almost empty based on the reading out of word, wy+1. the discrete pae flag goes low to show that q24 of d5 is almost empty based on the reading of wy+1. *h* word, wx is written into q8 of d3.
54 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits rclk oe *g* w d - m + 2 t a *i* t a d0 q31 w 0 d6 q2 *f* t qh t qs d0 q31 111 xxx00 d7 quad 1 110 00010 *d* *e* t ah t as t sth t sts d6q2 w d-m+1 t a w x +1 prev. q t olz ren raden estr wradd t ah 000 11111 t as rdadd d0q31 *a* *b* 000 xxx11 t qh t qs t sth t sts 5998 drw36 0xxx xxxx d0quad4 *bb* *cc* *dd* *ee* *ff* t paflz 1xxx xxxx d0quad4 d0quad4 t paf t paf 0xxx xxxx 0xxx xxxx d0quad4 1xxx xxxx d0quad4 d0quad4 0xxx xxxx t pafhz high-z high-z t paflz t waf *aa* device 0 paf n bus paf n d x quad y prev. paf n d x quad y device 0 paf qout w x prev. q d0 quad4 fstr t a wclk t skew3 23 d0 q31 wen t ens t enh waden t qh t qs t ah t as t ah t as din t ds t dh t ds t dh t ds t dh word w y d0 q31 w y+1 d0 q31 w y+2 d0 q31 *c* t ah t as *h* 1 high - z *gg* figure 31. paf n - direct mode, flag operation cycle: *a* queue 31 of device 0 is selected for read operations. the last word in the output register is available on qout. oe was previously taken low so the output bus is in low-impedance. *aa* quadrant 4 of device 0 is selected for the paf n bus. the bus is currently providing status of a previously selected quadrant, quad y of device x. *b* no read operation. *bb* queue 31 of device 0 is selected on the write port. *c* word, wx+1 is read out from the previous queue due to the fwft effect. *cc* paf n continues to show status of quad4 d0. the paf n bus is updated with the quadrant selected on the previous cycle, d0 quad 4. paf [7] is low showing the status of queue 31. the paf n outputs of the device previously selected on the paf n bus go to high-impedance. *d* a new quadrant, quad 1 of device 7 is selected for the paf n bus. word, wd-m+1 is read from q31 d0 due to the fwft operation. this read is at the paf n boundary of queue d0 q31. this read will cause the paf [7] output to go from low to high (almost full to not almost full), after a delay t skew3 + wclk + tpaf. if t skew3 is violated add an extra wclk cycle. *dd* no write operation. *e* no read operations occur, ren is high. *ee* paf [7] goes high to show that d0 q31 is not almost empty due to the read on cycle *c*. the active queue paf flag of device 0 goes from high-impedance to low-impedance. word, wy is written into d0 q31. *f* queue 2 of device 6 is selected for read operations. *ff* word, wy+1 is written into d0 q31. *g* word, wd-m+2 is read out due to fwft operation. *gg* paf [7] and the discrete paf flag go low to show the write on cycle *dd* causes q31 of d0 to again go almost full. word, wy+2 is written into d0 q31. *h* no read operation. *i* word, w0 is read from q0 of d6, selected on cycle *f*, due to fwft.
55 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges wclk 5998 drw37 t fsync t fsync fsync 0 (master) fxo 0 / fxi 1 t fxo t fxo t fsync t fsync fsync 1 (slave) fxo 1 / fxi 2 t fxo t fxo t fsync t fsync fsync 2 (slave) fxo 2 / fxi 0 t fxo t fxo paf n t paf t paf t paf t paf t paf t paf t paf t paf t paf t paf t paf t paf t paf t paf t fsync t fsync d0quad1 d0quad2 d0quad3 d0quad4 d1quad1 d1quad2 d1quad3 d1quad4 d2quad1 d2quad2 d2quad3 d2quad4 d0quad1 d0quad2 figure 32. paf n bus - polled mode note: 1. this diagram is based on 3 devices connected in expansion mode.
56 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits rclk 5998 drw38 t esync t esync esync 0 exo 0 / exi 1 t exo t exo t esync t esync esync 1 exo 1 / exi 2 t exo t exo t esync t esync esync 2 exo 2 / exi 0 t exo t exo pae n t pae t pae t pae t pae t pae t pae t pae t pae t pae t pae t pae t pae t pae t pae t esync t esync d0quad1 d0quad2 d0quad3 d0quad4 d1quad1 d1quad2 d1quad3 d1quad4 d2quad1 d2quad2 d2quad3 d2quad4 d0quad1 d0quad2 figure 33. pae n/ pr n bus - polled mode note: 1. this diagram is based on 3 devices connected in expansion mode.
57 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges figure 34. power down operation notes: 1. all read and write operations must have ceased a minimum of 4 wclk and 4 rclk cycles before power down is asserted. 2. when the pd input becomes deasserted, there will be a 1 s waiting period before read and write operations can resume. all input and output signals will also resume after this time period. 3. set-up and configuration static inputs are not affected during power down. 4. serial programming and jtag programming port are inactive during power down. 5. rcs = 0, wcs = 0 and oe = 0. these signals can toggle during and after power down. 6. all flags remain active and maintain their current states. 7. during power down, all outputs will be in high-impedance. 5998 drw39 wclk wen d[39:0] rclk ren q[39:0] pd erclk eren t ds t dh t dh t dh t ds 12 3 4 (1) t a t a t a t erclk t eren t ds 1ns t pdhz (7) t pdlz (2) t a t pdl t pdh (2) t pdh (2) t eren w dh w ds hi-z hi-z w d4 w d3 w d2 w d1 w d10 w d11 w d12 w d13 t ds hi-z
58 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits wradd waden wclk wen fstr paf n fsync ff paf sclk rclk ren estr pae n esync ov pae rdadd raden so fxo exo si fxi exi wradd waden wclk wen fstr paf n fsync ff paf sclk rclk ren estr pae n esync ov pae rdadd raden so fxo exo si fxi exi wradd waden wclk wen fstr paf n fsync ff paf sclk rclk ren estr pae n esync ov pae rdadd raden seno fxo exo q 0 -q 35 si fxi exi data bus write clock write enable write queue select full strobe programmable almost full write address full sync1 full flag almost full flag serial clock output data bus read clock read enable read queue select empty strobe programmable almost empty read address empty sync 1 output valid flag almost empty flag serial programming data input device 1 device 2 device n full sync2 empty sync 2 full sync n empty sync n seno seni done 5998 drw40 d 0 -d 35 q 0 -q 35 d 0 -d 35 d 0 -d 35 q 0 -q 35 seni pr packet reads pr pr serial enable seno seni figure 35. multi-queue expansion diagram notes: 1. if devices are configured for direct operation of the paf n/ pae n flag busses the fxi/exi of the master device should be tied low. all other devices tied high. the fxo/exo outputs are dnc (do not connect). 2. q outputs must not be mixed between devices, i.e. q0 of device 1 must connect to q0 of device 2, etc.
59 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges t a p tap cont- roller mux deviceid reg. boundary scan reg. bypass reg. clkdr, shiftdr updatedr tdo tdi tms tclk trst clklr, shiftlr updatelr instruction register instruction decode control signals 5998 drw41 jtag interface five additional pins (tdi, tdo, tms, tck and trst ) are provided to support the jtag boundary scan interface. the IDT72T51546/72t51556 incorporates the necessary tap controller and modified pad cells to implement the jtag facility. note that idt provides appropriate boundary scan description language program files for these devices. the standard jtag interface consists of four basic elements: ? ? ? ? ? test access port (tap) ? ? ? ? ? tap controller ? ? ? ? ? instruction register (ir) ? ? ? ? ? data register port (dr) the following sections provide a brief description of each element. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). the figure below shows the standard boundary-scan architecture figure 36. boundary scan architecture test access port (tap) the tap interface is a general-purpose port that provides access to the internal of the processor. it consists of four input ports (tclk, tms, tdi, trst ) and one output port (tdo). the tap controller the tap controller is a synchronous finite state machine that responds to tms and tclk signals to generate clock and control signals to the instruction and data registers for capture and update of data.
60 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits test-logic reset run-test/ idle 1 0 0 select- dr-scan select- ir-scan 1 1 1 capture-ir 0 capture-dr 0 0 exit1-dr 1 pause-dr 0 exit2-dr 1 update-dr 1 exit1-ir 1 exit2-ir 1 update-ir 1 1 0 1 1 1 5998 drw42 0 shift-dr 0 0 0 shift-ir 0 0 pause-ir 0 1 input = tms 0 0 1 figure 37. tap controller state diagram notes: 1. five consecutive tck cycles with tms = 1 will reset the tap. 2. tap controller does not automatically reset upon power-up. the user must provide a reset to the tap controller (either by trst or tms). 3. tap controller must be reset before normal queue operations can begin. refer to the ieee standard test access port specification (ieee std. 1149.1) for the full state diagram. all state transitions within the tap controller occur at the rising edge of the tclk pulse. the tms signal level (0 or 1) determines the state progression that occurs on each tclk rising edge. the tap controller takes precedence over the queue and must be reset after power up of the device. see trst description for more details on tap controller reset. test-logic-reset all test logic is disabled in this controller state enabling the normal operation of the ic. the tap controller state machine is designed in such a way that, no matter what the initial state of the controller is, the test- logic-reset state can be entered by holding tms at high and pulsing tck five times. this is the reason why the test reset ( trst ) pin is optional. run-test-idle in this controller state, the test logic in the ic is active only if certain instructions are present. for example, if an instruction activates the self test, then it will be executed when the controller enters this state. the test logic in the ic is idles otherwise. select-dr-scan this is a controller state where the decision to enter the data path or the select-ir-scan state is made. select-ir-scan this is a controller state where the decision to enter the instruction path is made. the controller can return to the test-logic-reset state other wise. capture-ir in this controller state, the shift register bank in the instruction register parallel loads a pattern of fixed values on the rising edge of tck. the last two significant bits are always required to be ?01?. shift-ir in this controller state, the instruction register gets connected between tdi and tdo, and the captured pattern gets shifted on each rising edge of tck. the instruction available on the tdi pin is also shifted in to the instruction register. exit1-ir this is a controller state where a decision to enter either the pause- ir state or update-ir state is made. pause-ir this state is provided in order to allow the shifting of instruction register to be temporarily halted. exit2-dr this is a controller state where a decision to enter either the shift- ir state or update-ir state is made. update-ir in this controller state, the instruction in the instruction register is latched in to the latch bank of the instruction register on every falling edge of tck. this instruction also becomes the current instruction once it is latched. capture-dr in this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of tck. shift-dr, exit1-dr, pause-dr, exit2-dr and update-dr these controller states are similar to the shift-ir, exit1-ir, pause-ir, exit2-ir and update-ir states in the instruction path.
61 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges the instruction register the instruction register allows an instruction to be shifted in serially into the processor at the rising edge of tclk. the instruction is used to select the test to be performed, or the test data register to be accessed, or both. the instruction shifted into the register is latched at the completion of the shifting process when the tap controller is at update- ir state. the instruction register must contain 4 bit instruction register-based cells which can hold instruction data. these mandatory cells are located nearest the serial outputs they are the least significant bits. test data register the test data register contains three test data registers: the bypass, the boundary scan register and device id register. these registers are connected in parallel between a common serial input and a common serial data output. the following sections provide a brief description of each element. for a complete description, refer to the ieee standard test access port specification (ieee std. 1149.1-1990). test bypass register the register is used to allow test data to flow through the device from tdi to tdo. it contains a single stage shift register for a minimum length in serial path. when the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of tclk when the tap controller is in the capture-dr state. the operation of the bypass register should not have any effect on the operation of the device in response to the bypass instruction. the boundary-scan register the boundary scan register allows serial data tdi be loaded in to or read out of the processor input/output ports. the boundary scan register is a part of the ieee 1149.1-1990 standard jtag implementation. the device identification register the device identification register is a read only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the tap in response to the idcode instruction. idt jedec id number is 0xb3. this translates to 0x33 when the parity is dropped in the 11-bit manufacturer id field. for the IDT72T51546/72t51556, the part number field contains the following values: device part# field (hex) IDT72T51546 0x48c idt72t51556 0x48d jtag device identification register 31(msb) 28 27 12 11 1 0(lsb) version (4 bits) part number (16-bit) manufacturer id (11-bit) 0x0 0x33 1 jtag instruction register the instruction register allows instruction to be serially input into the device when the tap controller is in the shift-ir state. the instruction is decoded to perform the following: ? ? ? ? ? select test data registers that may operate while the instruction is current. the other test data registers should not interfere with chip operation and the selected data register. ? ? ? ? ? define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. the instruction register is a 4 bit field (i.e. ir3, ir2, ir1, ir0) to decode 16 different possible instructions. instructions are decoded as follows. jtag instruction register decoding hex instruction function value 00 extest select boundary scan register 01 sample/preload select boundary scan register 02 idcode select chip identification data register 04 high-impedance jtag 0f bypass select bypass register the following sections provide a brief description of each instruction. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). extest the required extest instruction places the ic into an external boundary- test mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. as such, the extest instruction is the workhorse of ieee. std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. idcode the optional idcode instruction allows the ic to remain in its functional mode and selects the optional device identification register to be connected between tdi and tdo. the device identification register is a 32-bit shift register containing information regarding the ic manufacturer, device type, and version code. accessing the device identification register does not interfere with the operation of the ic. also, access to the device identification register should be immediately available, via a tap data-scan operation, after power-up of the ic or after the tap has been reset using the optional trst pin or by otherwise moving to the test-logic-reset state. sample/preload the required sample/preload instruction allows the ic to remain in a normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register can be accessed via a date scan operation, to take a sample of the functional data entering and leaving the ic. this instruction is also used to preload test data into the boundary-scan register before loading an extest instruction.
62 commercial and industrial temperature ranges IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits high-impedance the optional high-impedance instruction sets all outputs (including two-state as well as three-state types) of an ic to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between tdi and tdo. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the ic outputs. bypass the required bypass instruction allows the ic to remain in a normal functional mode and selects the one-bit bypass register to be connected between tdi and tdo. the bypass instruction allows serial data to be transferred through the ic from tdi to tdo without affecting the operation of the ic.
63 IDT72T51546/72t51556 2.5v, multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 and 2,359,296 bits commercial and industrial temperature ranges t 4 t 3 tdo tdo tdi/ tms tck trst t do notes to diagram: t1 = t tcklow t2 = t tckhigh t3 = t tckfall t4 = t tckrise t5 = trst (reset pulse width) t6 = trsr (reset recovery) 5998 drw43 t 5 t 6 t 1 t 2 t tck t dh t ds figure 38. standard jtag timing system interface parameters parameter symbol test conditions min. max. units jtag clock input period t tck - 100 - ns jtag clock high t tckhigh -40-ns jtag clock low t tcklow -40-ns jtag clock rise time t tckrise --5 (1) ns jtag clock fall time t tckfall --5 (1) ns jtag reset t rst -50-ns jtag reset recovery t rsr -50-ns jtag ac electrical characteristics (v cc = 2.5v 5%; tcase = 0 c to +85 c) IDT72T51546 idt72t51556 parameter symbol test conditions min. max. units data output t do (1) -20ns data output hold t doh (1) 0-ns data input t ds t rise=3ns 10 - ns t dh t fall=3ns 10 - note: 1. 50pf loading on external output signals. note: 1. guaranteed by design.
corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1533 santa clara, ca 95054 fax: 408-492-8674 email: flow-controlhelp@idt.com www.idt.com 64 plastic ball grid array (pbga, bb256-1) commercial (0 c to +70 c) industrial (-40 c to +85 c) low power 5998 drw44 commercial only commercial and industrial l idt xxxxx device type x power xx speed x package x process / temperature range blank i (1) 72t51546 1,179,648 bits ? 2.5v multi-queue flow-control device 72t51556 2,359,296 bits ? 2.5v multi-queue flow-control device clock cycle time (t clk ) speed in nanoseconds bb 5 6 ordering information note: 1. industrial temperature range product for the 6ns is available as a standard device. all other speed grades available by spec ial order. datasheet document history 06/06/2003 pgs. 1 through 64. 11/06/2003 pgs. 1, 4, 17 and 18.

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